# Advanced Packaging & CoWoS Capacity

Canonical URL: https://menfem.com/kb/hardware/concepts/advanced-packaging-cowos
Knowledge base topic: [Hardware & Computing](https://menfem.com/kb/hardware)
Frontier status: active
Tags: cowos, advanced-packaging, tsmc, bottlenecks, ai-supply-chain, hbm, chiplet

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The binding constraint on AI accelerator supply is no longer transistor density. It is **the ability
to bond HBM stacks to a logic die** — TSMC's CoWoS (Chip-on-Wafer-on-Substrate) family and its
equivalents. A Rubin-class accelerator is not one chip; it is a logic die plus 8 HBM stacks on an
interposer, and the interposer line is the narrowest part of the pipe. This is why the LENS treats
packaging as load-bearing as the logic node, and why any AI-compute narrative that omits it is
structurally incomplete.

## The capacity ramp

| Period | TSMC CoWoS capacity (wafers/month) | Source / as-of |
|---|---|---|
| Late 2024 | ~35,000 | Feb-2026 analysis |
| End of 2025 | ~75,000 (roughly doubled) | Feb-2026 analysis |
| End of 2026 (**projected**) | **120,000–140,000** (was a flat 130K target in Feb; a 120–140K band as of Jun-2026) | TrendForce, as-of 2026-06-15 |

**Every 2026 figure here is a projection, not a shipped number.** The flat 130K "target" was
reported in February 2026; a June-2026 TrendForce refresh (as-of 2026-06-15) revises it to a
**120–140K/mo band** and adds a supply-demand-gap metric (below). This KB has **not** verified
realized capacity against either — announced ≠ under construction ≠ delivered. The realized figure
would come only from a TSMC primary quarterly management report.

Named facilities in the expansion: **AP6 (Zhunan)** — existing advanced backend, process refinement;
**AP7 (Chiayi)** — positioned to become the largest advanced-packaging site; **AP8 (Tainan)** — newly
acquired footprint expansion. A further **advanced-packaging fab for Arizona** was announced at the
April 2026 NA Tech Symposium, putting packaging (not just wafer fab) into the US onshoring story.

## The June-2026 refresh: a gap that is narrowing, not widening

*All figures below are TrendForce / press projections with an explicit **as-of date of 2026-06-15**,
citing Economic Daily News / Reuters / Commercial Times — analysis-tier, not realized/audited output.*

The first quantified signal that the packaging constraint may **ease into 2027 rather than tighten**:

- **TSMC CoWoS (end-2026):** 120,000–140,000 wafers/mo (the KB's earlier 130K target now sits inside
  this band, four months later).
- **OSAT partners (end-2026):** 50,000–60,000 wafers/mo.
- **Combined industry (end-2026):** approaching ~200,000 wafers/mo.
- **Supply-demand gap:** narrowing from **~20% today → ~10% by end-2026**; TrendForce expects the
  severe 2.5D packaging shortage to begin **moderating in 2027**.
- **Expansion trajectory:** TSMC targeting >60% CoWoS capacity expansion by 2027; CoWoS CAGR >80%
  across 2022–2027.

A gap narrowing 20%→10% is a *projection about a projection* — a forecast supply level chasing a
forecast demand level — so it carries the softest evidence on this page. But the direction matters:
for the first time a third-party read has the constraint loosening rather than tightening, which is
the read-through the memory-scarcity cost models are most sensitive to.

## CoPoS — the successor packaging node to track

The same June-2026 source introduces **CoPoS (panel-level packaging)** as the node after CoWoS:

- Material/equipment qualification: June 2026.
- Pilot production: mid-2027.
- Mass production: 2028–2029.
- **NVIDIA Feynman** expected as the first CoPoS customer.

No independent read on CoPoS yield or economics exists yet — it enters the KB as a named successor
with a timeline, nothing realized.

## A second packaging axis: UCIe chiplet meshes (AMMA datapoint)

CoWoS bonds **one logic die to HBM stacks** on an interposer — the capacity this page tracks is the
capacity to do that specific bond. A structurally different packaging demand is emerging alongside it:
**multi-chiplet meshes of many small dies**, interconnected die-to-die rather than
die-to-interposer-to-HBM. **AMMA**
([arXiv:2604.26103](../../raw/amma-multichiplet-memory-centric-1m-context-attention.md), UC San
Diego / Columbia / Yonsei / NVIDIA / Samsung Semiconductor) is the clearest datapoint this KB holds
for what that looks like: **16 HBM-PNM cubes in a 4×4 2D mesh, connected by UCIe 3.0 D2D links**
(15 ns/hop, 1,500 GB/s per link), aggregating to **44 TB/s package bandwidth at 240 W** — a
memory-centric package where compute chiplets are replaced by memory-with-logic chiplets entirely,
rather than paired one-to-one with a central GPU die.

This is not CoWoS demand and does not compete with the wafer counts above — AMMA is a simulated
research architecture, not a shipping package. But it is a second axis worth tracking alongside the
CoWoS wafer count: **if memory-centric multi-chiplet designs like AMMA move toward productization,
the packaging bottleneck generalizes from "HBM stacks per interposer" to "D2D link count and UCIe
bandwidth per package"** — a different capacity model than the one TSMC discloses today. No
production UCIe 3.0 multi-chiplet package of this kind exists yet; treat this as a paper-design
datapoint, not a demand signal to size. See [Processing-In-Memory](./processing-in-memory.md) for the
full near-memory architecture spectrum this sits inside.

## Allocation is the real story

- **NVIDIA has reserved the majority of TSMC's most advanced packaging capacity**, reported at
  roughly **60%** of CoWoS through the expansion. AMD, Broadcom and the hyperscaler ASIC programs
  queue behind it — meaning packaging allocation, not design merit, partly determines who can ship in
  a given year ([CNBC](../../raw/nvidia-tsmc-advanced-packaging-reservation-2026.md),
  [CoWoS ramp](../../raw/tsmc-cowos-130k-wafers-late-2026.md)).
- **CoWoS-L and CoWoS-S were reported fully booked through 2026**, with OSAT partners (ASE, via
  CoWoP) absorbing overflow — the first sign that the constraint is spilling out of TSMC's own
  backend into the broader packaging supply chain.
- **"CoWoS sold out through 2027"** appears in TSMC call/slide material carried into the entity page
  as *attributed, not primary* — it has not been re-verified against a filing.

This is the sharp edge of the custom-silicon argument. A hyperscaler can commission a competitive
logic die from Broadcom or Marvell and still not ship, because it is standing behind NVIDIA in the
same interposer queue at the same foundry ([Custom Silicon vs GPU](./custom-silicon-vs-gpu.md)).

## Two capacity gates, one accelerator

Packaging is one of a pair. An AI accelerator needs **both** an interposer slot **and** HBM supply,
and the two are gated by different suppliers on different schedules:

| Gate | Who controls it | 2026 state |
|---|---|---|
| **Advanced packaging (CoWoS)** | TSMC (+ OSAT overflow) | Projected to a 120–140K/mo band (Jun-2026); supply-demand gap ~20%→~10% by end-2026; majority reserved by NVIDIA |
| **HBM supply** | SK Hynix / Samsung / Micron | 2026 capacity reported pre-booked; HBM3E 12-Hi mainstream, HBM4 ramping H2 |

Because a shortage at *either* gate caps output, the capacity narrative has to be read jointly — see
[HBM4 Memory Architecture](./hbm4-memory-architecture.md) and [SK Hynix](../entities/sk-hynix.md).
The memory-scarcity cost models treat both as a single exogenous "memory premium"
([Memory Scarcity & Inference Economics](./memory-scarcity-inference-economics.md)), which is a
simplification worth remembering: they cannot distinguish a packaging constraint from a DRAM
constraint.

## Key Claims

- **CoWoS capacity ramp ~35K (late 2024) → ~75K (end 2025) → 120–140K wafers/month projected (end
  2026).** *Evidence: weak — analysis piece whose own ingest note records that WebFetch was blocked
  and the content is a search-snippet summary; the 2026 figure is a projection*
  ([CoWoS ramp](../../raw/tsmc-cowos-130k-wafers-late-2026.md),
  [Jun-2026 refresh](../../raw/tsmc-cowos-supply-demand-gap-narrowing-2026.md))
- **Supply-demand gap projected to narrow ~20% → ~10% by end-2026** (TSMC 120–140K + OSAT 50–60K ≈
  ~200K industry wafers/mo), with the 2.5D shortage "moderating" in 2027. *Evidence: weak —
  analysis-tier TrendForce projection, as-of 2026-06-15, a forecast supply level chasing a forecast
  demand level; not realized output* ([Jun-2026 refresh](../../raw/tsmc-cowos-supply-demand-gap-narrowing-2026.md))
- **CoPoS (panel-level) is the successor node: materials qualified Jun-2026, pilot mid-2027, MP
  2028–29, NVIDIA Feynman as first customer.** *Evidence: weak — single analysis projection, no
  independent yield/economics read* ([Jun-2026 refresh](../../raw/tsmc-cowos-supply-demand-gap-narrowing-2026.md))
- **NVIDIA has reserved the majority (~60%) of TSMC advanced packaging capacity.** *Evidence:
  moderate — reported by CNBC and corroborated in the CoWoS ramp piece, but no primary allocation
  disclosure exists* ([CNBC](../../raw/nvidia-tsmc-advanced-packaging-reservation-2026.md))
- **Advanced packaging, not fabrication, is the binding constraint on AI accelerator supply through
  2027.** *Evidence: moderate — consistent across multiple secondary sources; the direction is
  well-corroborated even where the numbers are not*
  ([CNBC](../../raw/nvidia-tsmc-advanced-packaging-reservation-2026.md))
- **CoWoS-L/S fully booked through 2026; OSAT partners absorbing overflow.** *Evidence: weak —
  summary-derived cross-reference* ([CoWoS ramp](../../raw/tsmc-cowos-130k-wafers-late-2026.md))
- **Three named AP facilities (AP6 Zhunan, AP7 Chiayi, AP8 Tainan) plus an announced Arizona
  advanced-packaging fab.** *Evidence: moderate*
  ([CoWoS ramp](../../raw/tsmc-cowos-130k-wafers-late-2026.md),
  [A13/N2U symposium](../../raw/tsmc-a13-n2u-na-tech-symposium-2026.md))
- **TSMC H1'26 capex US$26.80B against a $52–56B FY guide** — the spending that funds this expansion
  is primary and tracking the high end. *Evidence: strong (primary, TSMC IR)*
  ([TSMC Q2'26](../../raw/tsmc-2q26-earnings-print.md))
- **AMMA (research, not shipping) packages 16 HBM-PNM cubes in a UCIe-3.0-linked 4×4 mesh — 44 TB/s
  aggregate bandwidth at 240 W** — a datapoint for a memory-centric multi-chiplet packaging paradigm
  distinct from CoWoS's one-logic-die-plus-HBM-stacks model. *Evidence: moderate — preprint, simulated
  architecture, not a shipping package; full text ingested 2026-07-24*
  ([AMMA](../../raw/amma-multichiplet-memory-centric-1m-context-attention.md))

## Conflicts & unresolved

- **"Quadruple by late 2026" vs. the realized ramp.** The 130K target was published in February 2026;
  a June-2026 refresh widened it to a 120–140K band and attached a narrowing supply-demand gap — but
  it remains a projection. No source in this KB confirms realized capacity. The gap between announced
  packaging capacity and delivered packaging capacity is exactly the sort of thing the 2026 power
  buildout got wrong at a much larger scale — announced ≠ under construction.
- **A narrowing gap is a forecast, not an easing you can bank.** The 20%→10% figure is a projected
  supply level chasing a projected demand level; if 2026 accelerator demand runs hotter than
  TrendForce assumed, the gap need not narrow at all. Directionally useful, not a settled number.
- **~60% NVIDIA allocation is a reported number with no primary counterpart.** TSMC does not disclose
  per-customer packaging allocation; both sources for the 60% figure are secondary.

## Open Questions

- Did CoWoS actually reach the projected 120–140K wafers/month by end-2026, and what is the realized
  figure vs the projection?
- Does the supply-demand gap actually narrow to ~10% by end-2026, or does hotter-than-modelled demand
  hold it near 20%?
- CoPoS: does the panel-level successor hit its mid-2027 pilot / 2028–29 MP timeline at usable yield,
  and does NVIDIA Feynman anchor it as projected?
- Does the OSAT overflow route (ASE CoWoP) carry real volume, or is it a pressure valve?
- Do AMD and the hyperscaler ASIC programs secure 2027 allocation, or pivot to alternate packaging
  (Foveros, hybrid bonding, panel-level)?
- Does the Arizona advanced-packaging fab change the geographic risk profile materially, or is it
  a token onshoring of the least-constrained step?
- Which gate binds harder in 2027 — interposer capacity or HBM supply?

## Related Concepts

- [HBM4 Memory Architecture](./hbm4-memory-architecture.md) — the thing being packaged; the second capacity gate
- [Rack-Scale AI Compute](./rack-scale-ai-compute.md) — packaged accelerators are the rack's atoms
- [Custom Silicon vs GPU](./custom-silicon-vs-gpu.md) — ASIC programs queue behind NVIDIA for the same interposers
- [Memory Scarcity & Inference Economics](./memory-scarcity-inference-economics.md) — treats packaging and DRAM as one exogenous premium
- [Processing-In-Memory & Memory-Centric Computing](./processing-in-memory.md) — AMMA's chiplet package is a memory-centric design; UCIe meshes are a second packaging axis alongside CoWoS

## Backlinks

*Pages that reference this concept:*
- [TSMC](../entities/tsmc.md)
- [NVIDIA reserves TSMC advanced packaging](../../raw/nvidia-tsmc-advanced-packaging-reservation-2026.md)
- [TSMC CoWoS 130K wafers](../../raw/tsmc-cowos-130k-wafers-late-2026.md)
- [TSMC CoWoS gap narrowing 20%→10% (Jun-2026)](../../raw/tsmc-cowos-supply-demand-gap-narrowing-2026.md)
- [AMMA — Multi-Chiplet Memory-Centric Attention](../../raw/amma-multichiplet-memory-centric-1m-context-attention.md)

## Changelog

- **2026-07-24** — Added **AMMA** (arXiv:2604.26103, full text) as a second packaging-paradigm
  datapoint: 16 HBM-PNM cubes in a UCIe-3.0-linked 4×4 mesh, 44 TB/s / 240 W package — a
  memory-centric multi-chiplet design distinct from CoWoS's one-logic-die-plus-HBM model. Research
  architecture, not a shipping package; not a CoWoS demand substitute. Cross-linked to
  Processing-In-Memory (added to `related`). Source already registered; added to this page's `sources`.
- **2026-07-23** — Added the **June-2026 TrendForce refresh** (as-of 2026-06-15): the flat 130K target becomes a **120–140K/mo band**, industry ~200K/mo incl. 50–60K OSAT, and a **supply-demand gap projected to narrow ~20%→~10% by end-2026** (first quantified signal the constraint may *ease* into 2027). Introduced **CoPoS** as the successor panel-level node (materials Jun-2026, pilot mid-2027, MP 2028–29, Feynman first customer). Held every figure as an analysis-tier PROJECTION with its as-of date; flagged the gap number as a forecast chasing a forecast. +1 source.
- **2026-07-22** — Initial compilation, consolidating CoWoS capacity material that had been scattered across frontier.md and the TSMC entity into a named concept. Recorded the 35K→75K→130K ramp as a **target** with its weak (search-snippet, WebFetch-blocked) provenance stated, the ~60% NVIDIA allocation as secondary-only, and the packaging↔HBM dual-gate framing.

## Sources

- tsmc-cowos-130k-wafers-late-2026
- tsmc-cowos-supply-demand-gap-narrowing-2026
- nvidia-tsmc-advanced-packaging-reservation-2026
- tsmc-2q26-earnings-print
- tsmc-2nm-a16-angstrom-era
- amma-multichiplet-memory-centric-1m-context-attention

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Cite as: MenFem Knowledge Base — https://menfem.com/kb/hardware/concepts/advanced-packaging-cowos