Rung 2 · Ready
Computer Architecture
Onur Mutlu · ETH Zürich · Fall 2023freeSource ↗Course schedule ↗
The active technical spine. The memory block (L2a, L9, L12–L15) is the physics behind the memory wall — every downstream claim about serving cost, HBM supply, or what a memory maker is worth is a claim about this material, so it is earned here or it is borrowed.
0 / 32 lectures
Progress
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Quota
Read it
Seat
Ready
State
The standing weekly technical slot.
Segments
The named subset — the scope above is the count| Ref | Title | Done | Artifacts | Note |
|---|---|---|---|---|
| L2a | Memory systems — the hierarchy | · | NBLABGMEBTL0/0 | Opens the memory rung. |
| L9 | DRAM fundamentals | · | NBLABGMEBTL0/0 | The HBM/Micron physics. |
| L12 | Memory organisation | · | NBLABGMEBTL0/0 | |
| L13 | DRAM operation | · | NBLABGMEBTL0/0 | |
| L14 | Row-buffer management | · | NBLABGMEBTL0/0 | |
| L15 | Memory controllers | · | NBLABGMEBTL0/1 |
Artifacts
Consume → do → output- The memory wall, derived rather than restated from a vendor deckNot yet — nothing has landed for this slot.
- Memory-hierarchy numbers, on a spaced scheduleNot yet — nothing has landed for this slot.