Research Frontier

Active Frontiers

0. Memory Scarcity as Market Structure — Active, contested

Status: One framework, one source, high leverage — treat as an argument to test | Key work: Matsuoka arXiv:2607.07207 (Jul 2026) + the desk's 22-page close read (Jul 2026)

The most consequential idea added to this topic in 2026 is that memory pricing has stopped being a component-cost input and become the thing that determines industry structure. Three pieces of it are worth carrying:

• $/PB (dollars per petabyte of bandwidth delivered) as a model-agnostic cost unit — but scoped strictly to saturated, bandwidth-bound decode.
• The depreciation conveyor — incumbents' fleets roll off 4-year amortization faster than hardware prices normalize, so the entrant/incumbent gap never closes inside the horizon (3.2× in 2026 → 1.9–2.0× in 2027 → 3–4× by 2029–30). This is a structural argument rather than a forecast, which is why it is the sturdiest thing here.
• The vintage-breakeven grid — a 16-cell result (4 vintages × 2 pricing regimes × 2 HBM branches). 2027 is robust in all four of its cells (7.5–11.1%); 2026 is worst under STICKY pricing (~31.3%), not coupled; 2029 (~37.6%) is nearly 2× as exposed as 2028 (~21.1%). The mechanism — coupled pricing is a ratio peg, sticky is an absolute peg, so they cross over as the incumbent floor collapses — is the genuinely derived contribution.

Provenance discipline is the whole story here. Single-author, non-peer-reviewed econ.GN preprint; its DRAM and HBM-wafer figures are TrendForce numbers it cites (summary-derived twice over); the headline "2–3×/yr demand growth" is asserted after a qualitative bias list with no decomposition; the 25/34/41 custom-silicon outcome split is elicited subjective probability, not model output; and the whole §6 verdict hangs on an unsourced 10–20% "plausible premium share" band. The author directs Japan's national supercomputing centre and the paper's inelastic-floor and architectural conclusions align with that position (RIKEN R-CCS). Full accounting on Memory Scarcity & Inference Economics.

What to watch: The "tokens growing while dollars stall" crash signature in Q3'26 hyperscaler disclosures. Whether the 10–20% premium band survives contact with platform revenue data. The reallocation channel (on-prem + sovereign inference) sized in dollars rather than anecdotes. Whether anyone reproduces the vintage grid with a realistic utilization distribution instead of 100% uptime.

0b. KV Cache as a First-Order Memory Object + Phase-Aware Inference — Rapid progress

Status: The software/hardware seam that decides serving economics | Key work: KV-cache management survey arXiv:2607.02574 (Jun 2026), TokenStack arXiv:2605.05639 (May 2026), Argonne prefill/decode evaluation arXiv:2606.17104 (Jun 2026)

Three 2026 papers converge on one reframing: the KV cache is a durable memory object with locality, lifetime, ownership and substrate — not a per-request scratch tensor — and it is what makes decode memory-bound.

• The map: 30+ KV-management systems collapse into five archetypes (local-paged, disaggregated-pipeline, shared-store, memory-pool, hybrid-tier). Once workload and hardware are fixed, ownership explains much of the remaining design variance. The survey also names seven missing KV-specific measurements — an explicit evaluation-methodology gap list, which for a KB drowning in vendor benchmarks is worth more than another benchmark.
• The hardware answer: TokenStack puts PIM logic only where hot KV lives, using the HBM4 logic base die as a stack-local controller — 1.62× throughput, 1.70× SLO capacity, 30–47% lower per-token energy vs AttAcc. This gives C-HBM4E level-3 near-memory compute its first named, large workload.
• The measurement discipline: GPUs consistently win compute-bound prefill; GroqRack wins memory-bound decode TPOT at small batch (batching unsupported); GPUs regain decode throughput as batch grows. Accelerator advantage is phase- and metric-dependent — "which is faster" is not a well-formed question.

All three are abstract-level in this KB — verified against arXiv, full text not ingested, no raw files. No magnitudes should be quoted from the Argonne study.

Two July-2026 additions extend the frontier along both axes: on hardware, AMMA (arXiv:2604.26103) pushes memory-centrism to its limit — it removes the GPU compute die from decode attention entirely, replacing it with HBM-PNM cubes (15.5× lower attention latency vs H100 at 1M context) and names Rubin's GPU-LPU platform as the baseline it argues against. On software, C²KV (arXiv:2607.17715) attacks the storage/transfer cost of the KV object directly — a position-agnostic, composable + compressed KV manifold that makes non-prefix KV blocks reusable without accuracy collapse (up to 17× long-context speedup). The two layers compound: a smaller, reusable KV cache changes what a KV-targeted PIM stack has to hold.

What to watch: Full-text ingest of the three core papers (top priority). Whether any memory maker roadmaps a heterogeneous-layer or KV-targeted PIM stack (SK Hynix's StreamDQ is the closest signal so far — base-die dequant, not KV, but same base-die-compute bet). Whether hyperscaler ASIC programs publish phase-separated benchmarks. Whether GroqRack's decode advantage survives batching support. Whether AMMA's GPU-free attention chiplet attracts any silicon commitment or stays academic.

1. Logical-Qubit Quantum Error Correction — Breakthrough

Status: Below threshold + break-even both crossed across two architectures | Key work: Willow (Aug 2024), Besedin lattice surgery (Jan 2026), IBM qLDPC (Nov 2025), Quantinuum iceberg (Mar 2026)

Four anchor results now define the QEC substrate:

• Google Willow: Λ=2.14 error suppression per 2 distance steps; d=7 surface code at 0.143% error/cycle; logical memory 2.4× physical.
• Besedin et al. (Nature Physics): first superconducting lattice surgery — the compute primitive on surface codes.
• IBM Nighthawk: 120 qubits, qLDPC real-time decoding <480ns (10× prior art).
• Quantinuum iceberg: 94 logical qubits from 98 physical, beyond break-even.

Three code families (surface / iceberg / qLDPC) are live on two qubit architectures (superconducting / trapped-ion) — and neutral atoms join as a third.

What to watch: Which architecture reaches full fault tolerance first. Postselection scaling in iceberg codes. Whether qLDPC decoders run on commodity hardware or custom ASICs. Lattice surgery extended to distance-5, 7, 9 on superconducting.

2. Neutral Atom Quantum Computing — Breakthrough

Status: Third-architecture emergence | Key work: Google+QuEra Apr 2026 expansion; Pasqal 2 logical qubits; QuEra to AIST Japan

Google formally entered neutral-atom computing in April 2026 via strategic investment in QuEra and an internal program led by Adam Kaufman (CU Boulder). This joins Microsoft + Atom Computing and independent Pasqal. 100,000 atoms per vacuum chamber is the medium-term scaling target — an order of magnitude beyond superconducting or trapped-ion. Optical-tweezer arrays enable dynamic connectivity that surface codes were never designed for.

What to watch: Pasqal's 250-qubit quantum-advantage attempt (H1 2026). Gate fidelity improvements toward superconducting/trapped-ion parity. Error-correction codes optimized for dynamic atomic-array connectivity. Whether Google's dual-modality dilutes or hedges focus.

3. Photonic Neural Network — Breakthrough

Status: 2026 as the production-substrate transition | Key work: imec iSiPP50G PTP (Nature Commns 2026), Ashtiani Nokia Bell Labs (Nature 2026), Lightmatter 2025

Three results flipped photonic computing from "someday substrate" to "we know how to build this": (1) imec's PyTorch-integrated tensor processor with pretrained-network compatibility, (2) Ashtiani et al.'s first end-to-end on-chip backprop training, (3) Lightmatter running unmodified BERT/ResNet/Atari at near-FP32 accuracy. Each solves a distinct gap: manufacturability, training, production workloads.

What to watch: Can a single chip integrate production scale + on-chip training + manufacturability? Yield at ~1M photonic components per chip. When a hyperscaler commits procurement dollars to photonic accelerators. Photonic equivalent of HBM (memory that's photonic-accessible).

4. TSMC Angstrom Era (N2 + A16) — Breakthrough

Status: N2 in volume; A16 late 2026 | Key work: TSMC Angstrom Era analysis (Jan 2026)

First Nanosheet GAA transistors in mass production — 10-15% speed / 25-30% power improvement over N3E. A16 (1.6nm) adds Super Power Rail backside power delivery, targeting late 2026 for NVIDIA Feynman. First architectural shift in over a decade.

N2-ramp status now primary (TSMC Q2'26, reported 2026-07-16): 2nm was 3% of TSMC wafer revenue in Q2'26; days-of-inventory rose 7 (to 87) "primarily due to N2 ramp," and the CFO flagged "the steep ramp-up of our 2-nanometer technology" into Q3. The guided N2-ramp margin dilution (2-3pt) plus overseas-fab dilution (2-4pt) is demonstrably active this quarter — yet TSMC gross margin still rose +1.5pp QoQ through the top of its guided band (67.7% vs a 65.5-67.5% guide). The ramp is real and dilutive on schedule; utilization/cost is currently outrunning it (TSMC Q2'26 print).

What to watch: Samsung GAA competitive response. Apple A20 in iPhone 18 as first consumer N2 product. Broadcom/Marvell custom ASICs for hyperscalers. A14 (1.4nm, ~2028) High-NA EUV economics. Whether the H2 N2 ramp (Q3 GM guided down to 65-67%) bends TSMC's margin as the guided dilution schedule implies.

5. HBM Memory Architectural Shakeup — Breakthrough

Status: HBM4 in production; HBM4E/C-HBM4E development | Key work: HBM4 Shakeup (Tom's Hardware Dec 2025)

Base dies moved from DRAM to TSMC logic processes (12FFC / N5 / N3P). Interface doubled to 2,048 bits; bandwidth at 22 TB/s per GPU (Rubin) scales to 3 TB/s per HBM4E stack. C-HBM4E introduces custom base dies with optional near-memory compute.

Supply mix — the commercially important correction. The generation that actually ships the volume in 2026 is HBM3E 12-Hi 36GB (~2/3 of 2026 HBM shipments), not HBM4; HBM4 16-Hi 48GB production was targeted for Q4 2026, with SK Hynix at ~60% share and its 2026 capacity reportedly pre-booked by NVIDIA + OpenAI — i.e. new entrants are supply-gated until 2027 regardless of design merit. This is a January 2026 third-party outlook and is now six months stale; the raw ingest is a search-snippet summary (WebFetch was blocked) and its "three market headwinds" were never captured. See SK Hynix.

The KB has no primary memory-maker source at all. That is the single largest structural gap in this topic. It closes, or doesn't, in the next eight days: SK Hynix reports 2026-07-29, Samsung 2026-07-30 — both dates verified against primary filings this week.

What to watch: The 7/29 and 7/30 prints — HBM4 mix, ASP, capacity, allocation. NMC workload viability (now partially answered: hot-KV attention). TPU/Trainium HBM4 timeline vs NVIDIA. Software stack for topology-aware memory domains. Rubin Ultra 1 TB HBM4E deployment. Whether the ~90% DRAM price rise / 23% HBM wafer share figures survive contact with primary disclosure.

6. Rack-Scale AI Compute — Rapid Progress

Status: Full production (May 2026); shipments fall 2026 | Key work: NVIDIA Vera Rubin CES + full-production update + SemiAnalysis teardown

Shift from GPU-as-product to rack-as-product. Vera Rubin NVL72: 72 GPUs, 260 TB/s aggregate, cableless modular trays, 180-220 kW liquid-cooled. NVIDIA confirmed full production in late May 2026, with shipments beginning fall 2026 across 350+ factories / 30 countries ("AI factory engine," 10x agent throughput vs Grace Blackwell). First clouds: AWS, Google Cloud, Azure, OCI, CoreWeave, Lambda, Nebius, Nscale.

Roadmap correction: the discrete long-context Rubin CPX GPU (30 PFLOPS NVFP4, 128 GB GDDR7) was roadmapped Sept 2025 and cancelled at GTC 2026. Rubin Ultra (2027) stays: ~100 PFLOPS FP4, ~1 TB HBM4E, Kyber rack with 576 GPUs / 144 packages.

What to watch: First production-shipment deployments fall 2026 vs the "full production" claim. Hyperscaler custom rack designs. Open-source inference stack (Triton, vLLM) as wildcard on ASIC adoption. Whether the disaggregated long-context idea (GDDR7 prefill) re-appears after the CPX cancellation.

7. Custom Silicon vs GPU — Breakthrough

Status: ASICs reach 27.8% of 2026 AI server shipments; growth outpaces GPU for the first time | Key work: SemiAnalysis (Feb), TrendForce (Jan), Tom's Hardware state-of-play (May), Anthropic 1M-TPU (Oct 2025 → 2026)

Hyperscaler ASICs (TPU v7 Ironwood, Trainium 3, Maia 200, MTIA, OpenAI Titan) reshape the competitive landscape. 2026 is when the inflection became measurable in shipments, not just CAGR projections:

• TrendForce: ASICs = 27.8% of AI server shipments in 2026 (highest since 2023), GPUs = 69.7%. AI server shipments +28% YoY; top-5 NA CSP capex +44.6% ASIC-growth vs 16.1% GPU-growth (first year ASIC growth outpaces merchant GPU).
• Merchant duopoly: Broadcom ~60% (TPU/MTIA/Maia/Titan) + Marvell ~35% (Trainium/Maia) of the co-design market; Marvell projects ~$11B AI ASIC revenue in 2026. The arms dealers win regardless of which hyperscaler chip prevails.
• Demand anchor: Anthropic committed ~1M Google Ironwood TPUs + >1 GW capacity in 2026 (tens of billions), plus a ~5 GW Google/Broadcom expansion from 2027 — while still running Trainium + NVIDIA in parallel.

NVIDIA inference share projected to drop from 90% to 20-30% by 2028, but rack-level lock-in may prove more durable than chip-level CUDA lock-in — and GPU absolute volume keeps growing even as share erodes (GPUs still ~70% of the 2026 mix).

What to watch: Whether realized 2026 shipments hit the 27.8% ASIC share. Broadcom/Marvell co-design share stability (corroborate the 60/35 split vs investor materials). Ironwood/Trainium3/Maia 200 ramp vs schedule. Whether OpenAI Titan tapes out on time. Open-source inference stacks (Triton, vLLM) eroding CUDA lock-in.

8. Memory-Centric Computing / Processing-In-Memory — Active

Status: Commercial wedge via C-HBM4E NMC (2026–27); research foundation deep | Key work: Mutlu / SAFARI (ETH Zurich) synthesis (Apr 2026); HBM4 Architectural Shakeup (Dec 2025); Samsung HBM-PIM (Aquabolt-XL); SK Hynix AiM; UPMEM → Qualcomm (claim, verify)

The "AI compute shortage" is substantially a memory-movement shortage. 60–90% of total system energy in real workloads is data movement, not compute; data-center processors spend 80–90% of their time waiting for memory; DRAM access costs 800× a FP op and up to 64,000× including storage/sensors. The response is two-pronged: (1) Processing Near Memory — logic on HBM base dies (C-HBM4E level-3 NMC), bank-level processors (UPMEM), shipping PIM DRAM (Samsung HBM-PIM, SK Hynix AiM); (2) Processing Using Memory — exploiting DRAM's analog behavior for bulk copy (RowClone), bitwise ops (Ambit), and RNG, demonstrated on unmodified commodity DRAM by violating timing parameters.

Reliability scaling is forcing memory intelligence regardless. RowHammer (repeated-activation bit flips) is exploited in the wild; RowPress (long-held activation) induces flips with orders-of-magnitude fewer activations; column disturbance affects thousands of rows simultaneously. DDR5 ships activation counters; Self-Managing DRAM is the research endpoint (paper rejected 6× over 3.5 years before acceptance).

The bottleneck is paradigm, not physics. JEDEC (~390 member companies) rarely converges on radical interface changes, and the trillion-dollar processor-centric investment is entrenched. Mutlu frames this as a "Copernican Revolution" — decades to fully realize.

PIM now has candidate killer workloads AND a memory-maker in the ring (updated, Jul 2026). The standing objection to PIM was "compelling energy arithmetic, no workload." Three 2026 near-memory works now name concrete workloads for base-die compute, and they span the spectrum of how far the GPU is displaced:

• TokenStack (arXiv:2605.05639) — hot KV-cache attention during LLM decode; only hot KV blocks benefit from near-memory compute while weights, activations and cold KV need dense capacity and GPU-visible bandwidth. Vertical heterogeneity inside the stack, HBM4 logic base die as stack-local controller.
• StreamDQ (arXiv:2607.08993, SK Hynix) — inline weight dequantization (INT4/INT8/FP8→FP16/BF16) on the HBM base die, one DeQuantization Block per pseudo-channel controller, selected by a 3-bit sideband tag with no GPU ISA change. 7.08× GEMM / 90.23% energy / 54.68% end-to-end latency; 0.127 mm² + 0.355 W per DQB in 12 nm. This is the KB's first primary source from a memory maker — SK Hynix showing what it intends to put on a custom-HBM base die, which is a materially different signal from an academic proposal.
• AMMA (arXiv:2604.26103) — the aggressive end: removes the GPU compute die entirely from decode attention, replacing it with HBM-PNM cubes in a multi-chiplet package (~2× bandwidth; 15.5× lower attention latency vs H100 at 1M context).

Be precise about what this resolves: together they answer what C-HBM4E level-3 NMC is for (hot-KV attention and weight dequantization) and one of them (StreamDQ) is from an actual DRAM maker. It does not fully close the "commercial PIM product specs" gap: StreamDQ is a research preprint with simulated results, not a committed shipping product with a spec sheet, and TokenStack/AMMA are academic architectures on academic baselines (AttAcc / H100). The regime caveat is consistent across all three — near-memory wins concentrate in memory-bound / small-batch decode, and StreamDQ's own advantage shrinks at large batch.

What to watch: Whether any of SK Hynix / Samsung / Micron roadmaps a heterogeneous-layer or KV-targeted PIM stack. Whether a vertically heterogeneous stack is manufacturable at yield and thermally viable. UPMEM/Qualcomm acquisition primary-source verification and post-deal product roadmap. Samsung HBM-PIM and SK Hynix AiM production volumes and hyperscaler design wins. C-HBM4E NMC workload adoption beyond vector-DB / recommendation. CXL 3.x composable memory reference architectures. DDR6 spec drafts for any hint of CPU-memory interface flexibility. First RowPress exploit in the wild. Whether independent hyperscaler benchmarks (Meta, Microsoft) replicate the 60–90% data-movement energy figure. Any NVIDIA public architecture statement post-Rubin that treats memory as compute rather than bandwidth.

9. Foundry Roadmap & Lithography Economics — Breakthrough

Status: TSMC defers high-NA EUV; A13/N2U announced; advanced packaging now binding constraint | Key work: TSMC NA Tech Symposium (Apr 23), Bloomberg high-NA EUV deferral (Apr 22), CNBC advanced-packaging reservation (Apr 8), NVIDIA cuLitho expansion (Apr 23)

A coherent roadmap shift emerged across one week in April 2026:

• A13 (~1.3nm) + N2U announced at TSMC NA Tech Symposium — A13 production targeted for 2029 (AI/HPC), N2U a cost-down N2 for phones/laptops/mid-tier AI.
• High-NA EUV deferred. Kevin Zhang (TSMC Deputy COO): ~$400M per tool vs ~$200M for current EUV — economics don't yet pencil. TSMC's bet: squeeze more from installed EUV via process tricks + computational lithography.
• Advanced packaging is the new bottleneck. NVIDIA reserves the majority of TSMC's CoWoS capacity (~60% reported). Capacity, not transistor density, gates AI accelerator supply through 2027. The ramp — ~35K wafers/mo (late 2024) → ~75K (end 2025) → a 120–140K band for end 2026, across AP6 Zhunan / AP7 Chiayi / AP8 Tainan plus an announced Arizona AP fab — is now consolidated on Advanced Packaging & CoWoS Capacity. Refreshed Jun-2026 (TrendForce): the Feb 130K target is now a 120–140K/mo band; adding ~50–60K OSAT capacity, the combined industry approaches ~200K/mo, and the supply-demand gap is projected to narrow from ~20% to ~10% by end-2026, with the 2.5D shortage "moderating" in 2027 (>60% TSMC expansion by 2027, CAGR >80% 2022–27). First quantified signal the constraint may ease into 2027 rather than tighten. Successor node CoPoS (panel-level) qualifies materials Jun-2026, pilots mid-2027, mass-produces 2028–29 with NVIDIA Feynman as first customer. All still projections — announced ≠ realized; the capex funding it (H1'26 US$26.80B) is primary, the capacity/gap numbers are not (CoWoS Jun-2026 refresh).
• Power is the downstream twin of packaging. 12 GW of US data-center capacity was announced for 2026 completion against ~5 GW under construction — a 7 GW shortfall, with only ~1/3 of announced sites having broken ground, and interconnect queues (AEP: 24 GW committed vs 190 GW raw) rather than generation as the binding constraint. Same discipline as CoWoS: announced ≠ under construction ≠ energized. Carried on Rack-Scale AI Compute; depth lives in the datacenters and electrification topics.
• cuLitho is the softener. NVIDIA's GPU-accelerated computational lithography (deeper integration with ASML/TSMC/Synopsys) lets standard EUV approximate higher-resolution patterning — extending the life of installed-base EUV and reducing TSMC's need to buy high-NA tools.

The pattern: the AI scaling story has migrated up the supply chain. 2018–2023 was about compute (GPU, custom ASIC). 2024–2025 was about memory (HBM3E → HBM4 → C-HBM4E). 2026+ is about packaging and lithography economics — who controls CoWoS, who pays for high-NA, and how computational tooling extends the existing fleet.

Q2'26 earnings update (primary, reported 2026-07-15/16) — the capex-as-order-book chain, now with numbers:

• TSMC capex is now primary: Q2'26 capex US$15.70B (Q1 US$11.10B); H1 US$26.80B against the FY guide of $52-56B — tracking the high end (H2 is the heavier half) (TSMC Q2'26 print).
• ASML raised FY2026 guidance to €43-45B / 54-56% GM — a +20.5% midpoint step-up since the February 20-F, and confirmed intent to add +30% to its ~65-unit Low-NA EUV capacity for 2027 (further 30% under investigation for 2028) (ASML Q2'26, ASML entity). ASML's Q2 beat was a service/Installed-Base story, not new EUV systems — so it confirms revenue durability more than the forward EUV order book.
• The two moved in the same window, same direction — TSMC spending at the top of its range while ASML raises its guide by €7.5B is what a durable pipeline into 2027-28 looks like (mechanical observation, not a directional call; TSMC's specific dollars did not "cause" ASML's Q2 beat).
• Pricing tension surfaced: TSMC reportedly "pushing back on ASML's pricing plan" [attributed: The Information via FinancialJuice, 2026-07-16] — the toll fight inside the chain, flagged not verified.

What to watch: ASML high-NA bookings through Q4 2026 (Intel + Samsung as the marginal customers). Whether TSMC's FY26 capex is formally raised vs merely reaffirmed at the high end. The TSMC↔ASML pricing pushback (who bears the tool-cost toll). TSMC Arizona advanced-packaging fab construction pace. Whether Intel 18A's high-NA bet delivers a true performance lead vs N2/A16. Whether AMD/Broadcom secure CoWoS allocation in 2027 or pivot to alternate packaging (Foveros, hybrid bonding). Whether cuLitho's role extends to ILT for A13.

10. Quantum Fault Tolerance Roadmap — Active

Status: Concrete 2029 target | Key work: IBM roadmap (Nov 2025)

IBM's public milestones: verified quantum advantage end-2026, 1,000+ qubits + 15,000 gates by 2028, large-scale fault tolerance by 2029. Quantinuum and neutral-atom trajectories converge on similar timeframe.

What to watch: Which practical problem anchors "verified advantage." Historical AI-style timeline slippage risk. Whether three-way architecture diversification accelerates or slows the field.

Recent Breakthroughs

Knowledge Gaps

Areas where the KB needs more sources — suggested searches for next /kb discover. Ordered by how much a gap currently distorts what this topic can honestly claim.

Tier 1 — the KB is making claims it cannot support

• No primary memory-maker supply/pricing source exists yet. Narrowed 2026-07-23: the architecture side is no longer empty — StreamDQ (arXiv:2607.08993) is a technical paper authored entirely by SK Hynix engineers, the KB's first primary memory-maker source, showing what SK Hynix intends to build into a custom-HBM base die. But the load-bearing gap is supply, ASP, capacity and allocation, and that still traces to one stale January outlook plus TrendForce figures cited second-hand. SK Hynix, Samsung Memory and Micron are LENS-required named entities. Closes or doesn't on 2026-07-29 (SK Hynix) and 2026-07-30 (Samsung) — both next week. Suggested: SK Hynix + Samsung Q2 2026 earnings releases and presentation decks direct from IR; "Micron FQ3 2026 HBM sold out capacity".
• Full text of the 2026 inference-architecture papers. The three core papers arXiv:2607.02574 (KV survey), arXiv:2605.05639 (TokenStack) and arXiv:2606.17104 (Argonne prefill/decode) are abstract-level only — no raw files, no magnitudes. Specifically missing: what the seven missing KV measurements are; TokenStack's methodology and whether the AttAcc baseline is fair; the Argonne TTFT/TPOT numbers and the batch size at which the GPU decode crossover happens. AMMA (arXiv:2604.26103) [FULL-TEXT INGESTED 2026-07-24] — 16 HBM-PNM cubes in a 4×4 UCIe-3.0 mesh, 44 TB/s aggregate bandwidth at 240 W (vs H100's 3.35 TB/s / 700 W); 15.5× lower attention latency / 6.9× lower energy vs H100 at 1M context (also 1.1–2.5× vs Rubin, 1.4–3.4× vs NeuPIMs); DSE finding that per-cube compute saturates ~96 TFLOPS before bandwidth binds, with comms-reordering speedup scaling 2.7×→65.4× from 8K→1M tokens. C²KV (arXiv:2607.17715) [FULL-TEXT INGESTED 2026-07-24] — compression ratio 4× primary (8×/16× also evaluated), up to 17× long-context speedup, and C²KV-4× accuracy beats Full Recompute on MuSiQue (0.3587 vs 0.3198) and 2WikiMQA (0.4477 vs 0.4018). StreamDQ (arXiv:2607.08993) was read at HTML level (design + headline results captured) but the full evaluation methodology/workloads are not ingested. Still open: the KV survey (2607.02574), TokenStack (2605.05639), and the Argonne study (2606.17104) remain abstract-level with no raw files. Suggested: fetch those three PDFs directly and ingest properly.
• Realized CoWoS capacity vs the target. Refreshed 2026-07-23: a Jun-2026 TrendForce update (CoWoS refresh) revises the Feb 130K figure to a 120–140K/mo band and adds a supply-demand-gap metric (~20%→~10% by end-2026) — richer, fresher, but still a projection, not realized output. The realized number would come from TSMC's own quarterly management report; the gap stays open until then. Announced ≠ delivered. Suggested: "TSMC CoWoS capacity 2026 actual wafers per month earnings call"; TSMC quarterly management reports. New sub-gap: CoPoS (panel-level successor) — pilots mid-2027, MP 2028–29, Feynman first customer; no independent read on yield/economics. Suggested: "TSMC CoPoS panel-level packaging yield 2027".
• Independent replication of anything in arXiv:2607.07207. One single-author non-peer-reviewed preprint currently supplies this topic's entire inference-economics framework. Suggested: "inference cost per petabyte bandwidth model 2026"; "GPU vintage depreciation AI capex solvency analysis"; any peer-reviewed or sell-side model using a comparable unit.

Tier 2 — named entities and numbers the LENS requires

• Samsung Foundry / Intel Foundry competitive response — 2nm/18A yield, customer wins. Suggested: "Samsung 2nm GAA 2026 yield customer; Intel 18A production ramp".
• Micron — no entity page; the third HBM supplier and NVIDIA's named HBM4 volume partner. Suggested: "Micron HBM4 capacity 2026 sold out earnings".
• Broadcom / Marvell ASIC specifics — the ~60%/~35% co-design split and Marvell's ~$11B 2026 figure are summary-derived from one survey. Suggested: "Broadcom AVGO Marvell MRVL AI ASIC revenue 2026 investor day custom XPU".
• Hyperscaler ASIC chip-level specs — Maia 200 and Trainium3 full specs, OpenAI Titan architecture. Suggested: "Microsoft Maia 200 specs HBM; AWS Trainium3 3nm TFLOPS; OpenAI Titan ASIC".
• Top-4 hyperscaler 2026 capex totals — required numeric cell, still only carried as a "+40% YoY" aggregate. Suggested: Microsoft/Meta/Alphabet/Amazon Q2 2026 10-Qs.
• AMD MI400 Instinct 2026 — still entirely absent. Suggested: "AMD MI400 Helios rack 2026 TSMC N2 HBM4".
• Groq beyond one benchmark — architecture, capacity, customers, whether the batching gap is architectural. Suggested: "Groq LPU architecture SRAM inference 2026 capacity funding".

Tier 3 — standing technical gaps

• Commercial PIM product specs — narrowed again 2026-07-23: TokenStack answered what NMC is for (hot-KV attention) and StreamDQ adds a second workload (base-die weight dequantization) from an actual memory maker, SK Hynix — but it is still a research preprint with simulated results, not a shipping product with a spec sheet or a committed heterogeneous-layer-stack roadmap. Still needed: shipping product specs and a memory-maker public roadmap commitment. Suggested: "Samsung HBM-PIM Aquabolt-XL 2026; SK Hynix AiM GDDR6 GenAI benchmarks; SK Hynix custom-HBM base-die roadmap 2027; HBM4 PIM roadmap".
• PIM primary sources — Mutlu/SAFARI arXiv (RowClone, Ambit, Self-Managing DRAM, RowPress). Suggested: "Mutlu SAFARI RowHammer RowPress Self-Managing DRAM arXiv".
• UPMEM / Qualcomm acquisition — confirm claim + post-deal roadmap. Suggested: "UPMEM Qualcomm acquisition processing in memory DRAM".
• JEDEC DDR6 activation counter and interface flexibility. Suggested: "JEDEC DDR6 specification 2026 activation counter RowHammer".
• Memory-semantic fabric (CXL 3.x) — composable memory, disaggregation; the "memory-pool" KV archetype depends on it. Suggested: "CXL 3.0 composable memory 2026 AI".
• Chiplet standards (UCIe) — the standard is still missing. Datapoint added 2026-07-23: AMMA (arXiv:2604.26103) gives one multi-chiplet memory-centric architecture (HBM-PNM cubes, intra-package D2D link DSE) but does not cover the UCIe spec itself. Suggested: "UCIe 3.0 chiplet interconnect 2026 roadmap bandwidth".
• Edge AI chips — Apple Neural Engine, Qualcomm Hexagon, MediaTek APU. Relevant now as the on-prem/local-inference reallocation channel. Suggested: "edge AI chip 2026 on-device inference".
• Photonic equivalent of HBM — photonic-accessible memory. Suggested: "photonic memory on-chip bandwidth 2026".
• Pasqal neutral-atom quantum-advantage attempt results — H1 2026 target. Suggested: "Pasqal quantum advantage 250 qubit 2026 result".
• Atom Computing + Microsoft Phoenix details. Suggested: "Atom Computing Phoenix Azure Quantum 2026 benchmarks".
• Quantum advantage verification problem — which problem anchors "verified advantage"? Suggested: "verified quantum advantage 2026 problem cryptography sampling materials".

Closed this compile

• Data center power and cooling — 7 GW shortfall and interconnect-queue figures now carried on Rack-Scale AI Compute, though on weak (summary-derived) provenance; depth belongs to the datacenters topic.
• C-HBM4E NMC workload adoption — answered in principle by TokenStack (hot-KV attention); the production half moved to Tier 3 above.
• The three discovered-but-uningested arXiv papers — compiled 2026-07-22 at abstract level; full-text ingest promoted to Tier 1.