Research Frontier

Active Frontiers

1. Rack-Scale AI Compute — Rapid Progress

The shift from GPU-as-product to rack-as-product is accelerating. NVIDIA's Vera Rubin NVL72 packs 72 GPUs into a single rack with 260 TB/s aggregate bandwidth, cableless modular trays, and fully integrated networking/security/cooling. This represents a qualitative change in how AI infrastructure is designed and sold — the rack is the computer.

Key signals: Cableless modular design (5-min assembly), PCB area coverage increasing 2.3x, 180-220 kW liquid-cooled racks entering production H2 2026.

Confidence: High. Multiple data points from NVIDIA disclosure and independent SemiAnalysis teardown.

2. Custom Silicon vs GPU — Active

Hyperscaler ASICs (TPU v7, Trainium 3, Maia 200, MTIA) growing at 44.6% CAGR are reshaping the competitive landscape. NVIDIA's inference share projected to drop from 90% to 20-30% by 2028, but system-level lock-in through rack co-design may prove more durable than chip-level CUDA lock-in. The open-source inference stack (Triton, vLLM) is the key variable that could accelerate or slow ASIC adoption.

Key signals: Four major hyperscalers with advanced custom silicon programs. NVIDIA responding with system-level rather than chip-level differentiation.

Confidence: Moderate. Growth trajectory is clear; market share projections are speculative.

3. Memory Bandwidth Revolution (HBM4) — Rapid Progress

HBM4 delivers 22 TB/s bandwidth (2.8x over HBM3e) with 288 GB capacity. This is the memory generation that makes long-context inference and large MoE models viable at production scale. First deployment in Vera Rubin, with broader adoption expected 2026-2027.

Key signals: Rubin is first production HBM4 deployment. Memory bandwidth has been the primary inference bottleneck for two architecture generations.

Confidence: High. Hardware specifications confirmed by NVIDIA.

Knowledge Gaps

• Quantum computing — No sources ingested on quantum error correction, logical qubit milestones, or timeline to quantum advantage for practical workloads.
• Edge AI chips — No coverage of on-device inference ASICs (Apple Neural Engine, Qualcomm Hexagon, MediaTek APU) or the edge vs cloud compute balance.
• Chiplet standards — UCIe (Universal Chiplet Interconnect Express) and disaggregated chip architectures are missing from the knowledge base.
• Semiconductor supply chain — TSMC advanced node capacity, geopolitical risk (Taiwan), and packaging bottlenecks (CoWoS) not yet covered.
• Power and cooling infrastructure — Data center power constraints and liquid cooling deployment at scale deserve dedicated analysis.