Research Frontier

Active Frontiers

1. Logical-Qubit Quantum Error Correction — Breakthrough

Status: Below threshold + break-even both crossed across two architectures | Key work: Willow (Aug 2024), Besedin lattice surgery (Jan 2026), IBM qLDPC (Nov 2025), Quantinuum iceberg (Mar 2026)

Four anchor results now define the QEC substrate:

• Google Willow: Λ=2.14 error suppression per 2 distance steps; d=7 surface code at 0.143% error/cycle; logical memory 2.4× physical.
• Besedin et al. (Nature Physics): first superconducting lattice surgery — the compute primitive on surface codes.
• IBM Nighthawk: 120 qubits, qLDPC real-time decoding <480ns (10× prior art).
• Quantinuum iceberg: 94 logical qubits from 98 physical, beyond break-even.

Three code families (surface / iceberg / qLDPC) are live on two qubit architectures (superconducting / trapped-ion) — and neutral atoms join as a third.

What to watch: Which architecture reaches full fault tolerance first. Postselection scaling in iceberg codes. Whether qLDPC decoders run on commodity hardware or custom ASICs. Lattice surgery extended to distance-5, 7, 9 on superconducting.

2. Neutral Atom Quantum Computing — Breakthrough

Status: Third-architecture emergence | Key work: Google+QuEra Apr 2026 expansion; Pasqal 2 logical qubits; QuEra to AIST Japan

Google formally entered neutral-atom computing in April 2026 via strategic investment in QuEra and an internal program led by Adam Kaufman (CU Boulder). This joins Microsoft + Atom Computing and independent Pasqal. 100,000 atoms per vacuum chamber is the medium-term scaling target — an order of magnitude beyond superconducting or trapped-ion. Optical-tweezer arrays enable dynamic connectivity that surface codes were never designed for.

What to watch: Pasqal's 250-qubit quantum-advantage attempt (H1 2026). Gate fidelity improvements toward superconducting/trapped-ion parity. Error-correction codes optimized for dynamic atomic-array connectivity. Whether Google's dual-modality dilutes or hedges focus.

3. Photonic Neural Network — Breakthrough

Status: 2026 as the production-substrate transition | Key work: imec iSiPP50G PTP (Nature Commns 2026), Ashtiani Nokia Bell Labs (Nature 2026), Lightmatter 2025

Three results flipped photonic computing from "someday substrate" to "we know how to build this": (1) imec's PyTorch-integrated tensor processor with pretrained-network compatibility, (2) Ashtiani et al.'s first end-to-end on-chip backprop training, (3) Lightmatter running unmodified BERT/ResNet/Atari at near-FP32 accuracy. Each solves a distinct gap: manufacturability, training, production workloads.

What to watch: Can a single chip integrate production scale + on-chip training + manufacturability? Yield at ~1M photonic components per chip. When a hyperscaler commits procurement dollars to photonic accelerators. Photonic equivalent of HBM (memory that's photonic-accessible).

4. TSMC Angstrom Era (N2 + A16) — Breakthrough

Status: N2 in volume; A16 late 2026 | Key work: TSMC Angstrom Era analysis (Jan 2026)

First Nanosheet GAA transistors in mass production — 10-15% speed / 25-30% power improvement over N3E. A16 (1.6nm) adds Super Power Rail backside power delivery, targeting late 2026 for NVIDIA Feynman. First architectural shift in over a decade.

What to watch: Samsung GAA competitive response. Apple A20 in iPhone 18 as first consumer N2 product. Broadcom/Marvell custom ASICs for hyperscalers. A14 (1.4nm, ~2028) High-NA EUV economics.

5. HBM Memory Architectural Shakeup — Breakthrough

Status: HBM4 in production; HBM4E/C-HBM4E development | Key work: HBM4 Shakeup (Tom's Hardware Dec 2025)

Base dies moved from DRAM to TSMC logic processes (12FFC / N5 / N3P). Interface doubled to 2,048 bits; bandwidth at 22 TB/s per GPU (Rubin) scales to 3 TB/s per HBM4E stack. C-HBM4E introduces custom base dies with optional near-memory compute.

What to watch: NMC workload viability. TPU/Trainium HBM4 timeline vs NVIDIA. Software stack for topology-aware memory domains. Rubin Ultra 1 TB HBM4E deployment.

6. Rack-Scale AI Compute — Rapid Progress

Status: Production H2 2026 | Key work: NVIDIA Vera Rubin + SemiAnalysis teardown

Shift from GPU-as-product to rack-as-product. Vera Rubin NVL72: 72 GPUs, 260 TB/s aggregate, cableless modular trays, 180-220 kW liquid-cooled.

What to watch: First customer deployments H2 2026. Hyperscaler custom rack designs. Open-source inference stack (Triton, vLLM) as wildcard on ASIC adoption.

7. Custom Silicon vs GPU — Active

Status: ASICs at 44.6% CAGR | Key work: SemiAnalysis

Hyperscaler ASICs (TPU v7, Trainium 3, Maia 200, MTIA) reshape the competitive landscape. NVIDIA inference share projected to drop from 90% to 20-30% by 2028, but rack-level lock-in may prove more durable than chip-level CUDA lock-in.

8. Memory-Centric Computing / Processing-In-Memory — Active

Status: Commercial wedge via C-HBM4E NMC (2026–27); research foundation deep | Key work: Mutlu / SAFARI (ETH Zurich) synthesis (Apr 2026); HBM4 Architectural Shakeup (Dec 2025); Samsung HBM-PIM (Aquabolt-XL); SK Hynix AiM; UPMEM → Qualcomm (claim, verify)

The "AI compute shortage" is substantially a memory-movement shortage. 60–90% of total system energy in real workloads is data movement, not compute; data-center processors spend 80–90% of their time waiting for memory; DRAM access costs 800× a FP op and up to 64,000× including storage/sensors. The response is two-pronged: (1) Processing Near Memory — logic on HBM base dies (C-HBM4E level-3 NMC), bank-level processors (UPMEM), shipping PIM DRAM (Samsung HBM-PIM, SK Hynix AiM); (2) Processing Using Memory — exploiting DRAM's analog behavior for bulk copy (RowClone), bitwise ops (Ambit), and RNG, demonstrated on unmodified commodity DRAM by violating timing parameters.

Reliability scaling is forcing memory intelligence regardless. RowHammer (repeated-activation bit flips) is exploited in the wild; RowPress (long-held activation) induces flips with orders-of-magnitude fewer activations; column disturbance affects thousands of rows simultaneously. DDR5 ships activation counters; Self-Managing DRAM is the research endpoint (paper rejected 6× over 3.5 years before acceptance).

The bottleneck is paradigm, not physics. JEDEC (~390 member companies) rarely converges on radical interface changes, and the trillion-dollar processor-centric investment is entrenched. Mutlu frames this as a "Copernican Revolution" — decades to fully realize.

What to watch: UPMEM/Qualcomm acquisition primary-source verification and post-deal product roadmap. Samsung HBM-PIM and SK Hynix AiM production volumes and hyperscaler design wins. C-HBM4E NMC workload adoption beyond vector-DB / recommendation. CXL 3.x composable memory reference architectures. DDR6 spec drafts for any hint of CPU-memory interface flexibility. First RowPress exploit in the wild. Whether independent hyperscaler benchmarks (Meta, Microsoft) replicate the 60–90% data-movement energy figure. Any NVIDIA public architecture statement post-Rubin that treats memory as compute rather than bandwidth.

9. Foundry Roadmap & Lithography Economics — Breakthrough

Status: TSMC defers high-NA EUV; A13/N2U announced; advanced packaging now binding constraint | Key work: TSMC NA Tech Symposium (Apr 23), Bloomberg high-NA EUV deferral (Apr 22), CNBC advanced-packaging reservation (Apr 8), NVIDIA cuLitho expansion (Apr 23)

A coherent roadmap shift emerged across one week in April 2026:

• A13 (~1.3nm) + N2U announced at TSMC NA Tech Symposium — A13 production targeted for 2029 (AI/HPC), N2U a cost-down N2 for phones/laptops/mid-tier AI.
• High-NA EUV deferred. Kevin Zhang (TSMC Deputy COO): ~$400M per tool vs ~$200M for current EUV — economics don't yet pencil. TSMC's bet: squeeze more from installed EUV via process tricks + computational lithography.
• Advanced packaging is the new bottleneck. NVIDIA reserves the majority of TSMC's CoWoS capacity. Capacity, not transistor density, gates AI accelerator supply through 2027.
• cuLitho is the softener. NVIDIA's GPU-accelerated computational lithography (deeper integration with ASML/TSMC/Synopsys) lets standard EUV approximate higher-resolution patterning — extending the life of installed-base EUV and reducing TSMC's need to buy high-NA tools.

The pattern: the AI scaling story has migrated up the supply chain. 2018–2023 was about compute (GPU, custom ASIC). 2024–2025 was about memory (HBM3E → HBM4 → C-HBM4E). 2026+ is about packaging and lithography economics — who controls CoWoS, who pays for high-NA, and how computational tooling extends the existing fleet.

What to watch: ASML high-NA bookings through Q4 2026 (Intel + Samsung as the marginal customers). TSMC Arizona advanced-packaging fab construction pace. Whether Intel 18A's high-NA bet delivers a true performance lead vs N2/A16. Whether AMD/Broadcom secure CoWoS allocation in 2027 or pivot to alternate packaging (Foveros, hybrid bonding). Whether cuLitho's role extends to ILT for A13.

10. Quantum Fault Tolerance Roadmap — Active

Status: Concrete 2029 target | Key work: IBM roadmap (Nov 2025)

IBM's public milestones: verified quantum advantage end-2026, 1,000+ qubits + 15,000 gates by 2028, large-scale fault tolerance by 2029. Quantinuum and neutral-atom trajectories converge on similar timeframe.

What to watch: Which practical problem anchors "verified advantage." Historical AI-style timeline slippage risk. Whether three-way architecture diversification accelerates or slows the field.

Recent Breakthroughs

Knowledge Gaps

Areas where the KB needs more sources — suggested searches for next /kb discover:

• AMD MI400 Instinct 2026 — still absent; was C4 shortlist, not selected. Suggested: "AMD MI400 Helios rack 2026 TSMC N2 HBM4"
• Edge AI chips — Apple Neural Engine, Qualcomm Hexagon, MediaTek APU. Suggested: "edge AI chip 2026 on-device inference neural engine"
• Chiplet standards (UCIe) — missing. Suggested: "UCIe chiplet interconnect 2026 roadmap"
• Pasqal neutral-atom quantum-advantage attempt results — H1 2026 demonstration target. Suggested: "Pasqal quantum advantage 250 qubit 2026 result"
• Atom Computing + Microsoft Phoenix details — briefly mentioned but no deep source. Suggested: "Atom Computing Phoenix Azure Quantum 2026 benchmarks"
• Samsung / Intel foundry competitive response — 3nm / 2nm / 18A yield + customer wins. Suggested: "Samsung 2nm GAA 2026 yield customer; Intel 18A production"
• Data center power and cooling — electrical grid constraints; liquid cooling at 180+ kW per rack. Suggested: "data center power constraint AI 2026 liquid cooling grid"
• Memory-semantic fabric (CXL 3.0) — composable memory, disaggregation. Suggested: "CXL 3.0 composable memory 2026 AI"
• PIM primary sources — Mutlu/SAFARI arXiv (RowClone, Ambit, Self-Managing DRAM, RowPress). Suggested: "Mutlu SAFARI RowHammer RowPress Self-Managing DRAM arXiv"
• Commercial PIM product specs — Samsung HBM-PIM (Aquabolt-XL), SK Hynix AiM GDDR6. Suggested: "Samsung HBM-PIM Aquabolt-XL 2026; SK Hynix AiM GDDR6 GenAI benchmarks"
• UPMEM / Qualcomm acquisition — confirm claim + post-deal product roadmap. Suggested: "UPMEM Qualcomm acquisition processing in memory DRAM"
• JEDEC DDR6 activation counter and interface flexibility — any hint of CPU-memory protocol shift. Suggested: "JEDEC DDR6 specification 2026 activation counter RowHammer"
• Broadcom / Marvell ASIC specifics — named as Microsoft/Alphabet/Meta partners but no deep source. Suggested: "Broadcom Marvell hyperscaler custom AI ASIC 2026 deep dive"
• Photonic equivalent of HBM — memory that's photonic-accessible. Suggested: "photonic memory on-chip bandwidth 2026"
• Quantum advantage verification problem — which specific problem anchors "verified advantage"? Suggested: "verified quantum advantage 2026 problem cryptography sampling materials"