Build 06 · Open
Compute a DRAM access by hand, then check it against the spec
Work out the latency of a single memory access from the timing parameters — row activate, column access, precharge — and verify against a real datasheet.
Open
State
6 / 6
Route step
0
Notes
Time — about a week
Done when
A state a stranger could checkA hand-computed access time matches a published spec, and you can explain what a row-buffer hit changes.
Why it is harder — First build with no code at all. Pure derivation, checked against a primary document.
What it reads
Just enough to unblock the next step- Computer Architecture L12 · L13 · L14 · L15The four memory lectures. Verify their titles against the ETH schedule first — the registry and the retired study-plan disagree on L12 and L15.
What it ships
- NotebookThe memory wall, derived rather than restated from a vendor deck
- BottleDRAM timing parameters, spaced
Teach it back
If it cannot be explained plainly, it was not learned- 1Explain itExplain what you built to a friend who has never seen it. Plain words, no jargon, five sentences at most.
- 2Predicted vs realWhat you expected to happen, what actually happened, and why the two differ.
- 3Where it breaksThe question about it you still cannot answer, and the point where your explanation stops working.
- 4KeepThe one number, rule or picture worth keeping. It becomes a bottle and gets re-tested.
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