Custom Silicon Inflection 2026

Abstract

SemiAnalysis provides a deep technical teardown of NVIDIA's Vera Rubin NVL72 architecture, analyzing how the company's "extreme co-design" strategy — treating the entire rack as a distributed computing unit — creates a system-level moat that custom ASICs struggle to replicate, even as hyperscaler chip programs (Google TPU, Amazon Trainium, Microsoft Maia, Meta MTIA) grow rapidly.

Key Contributions

• Custom ASICs are growing at 44.6% CAGR vs GPU-based solutions at 16.1% CAGR — but this isn't eroding NVIDIA's dominance as much as headlines suggest
• NVIDIA's moat isn't the GPU chip alone — it's the co-designed rack: GPU + CPU + 4 networking chips + cooling + power delivery + software as one product
• Vera Rubin NVL72 moves from cable-intensive designs to cableless modular trays using Paladin HD2 connectors (assembly: 5 min vs 2 hours previously)
• PCB area coverage increases ~2.3x from GB300 to VR NVL72, driving up BoM costs but improving system density
• Rack power envelope: 180-220 kW requires purpose-built liquid cooling infrastructure

The Competitive Landscape

Custom ASIC Programs

• Google TPU v7 (Ironwood): Rack-scale design, targeting inference at scale
• Amazon Trainium 3: Third-generation custom training accelerator
• Microsoft Maia 200: Second-generation custom AI chip
• Meta MTIA: Custom inference accelerator
• Combined custom ASIC market growing at 44.6% CAGR

The GPU Counter-Argument

Despite ASIC growth, SemiAnalysis argues NVIDIA maintains advantages through:

1. System-level integration — No ASIC vendor matches the full-stack co-design (compute + networking + DPU + security)
2. Software ecosystem — CUDA, Triton, and framework support create switching costs
3. Generational cadence — Annual architecture updates vs multi-year ASIC development cycles
4. Inference market share projected to fall from 90%+ to 20-30% by 2028 for NVIDIA, but total market expands so absolute revenue grows

The ASIC Advantage

Custom ASICs win on:

• Cost efficiency for known, stable workloads (inference for specific model architectures)
• Power efficiency when optimized for narrow use cases
• Strategic independence from single-vendor lock-in

Key Data Points

• Rubin GPU: ~3.5x FP4 FLOPs vs Blackwell, 336B transistors (60% increase)
• Vera CPU: 88 cores (91 printed for yield), 2x performance over Grace, 2.5x memory bandwidth, 227B transistors (2.2x increase)
• NVLink 6 maintains 28.8T bandwidth per tray with doubled port rates
• PCB materials upgraded to M8/M9 CCL for signal integrity at higher speeds

Thesis

The GPU monopoly isn't ending — it's evolving. NVIDIA's response to custom silicon competition is to move up the stack, selling racks instead of chips. Custom ASICs capture the inference long-tail, but NVIDIA captures the premium training + cutting-edge inference market through system integration that no single-chip competitor can match.

Limitations

• SemiAnalysis has a premium subscription model — detailed BoM and power budget analysis behind paywall
• Analysis is NVIDIA-centric; may underweight the compounding effect of multiple hyperscalers investing billions annually in custom silicon
• Doesn't fully account for open-source software ecosystem (Triton, vLLM) potentially reducing CUDA lock-in

Source: Vera Rubin – Extreme Co-Design by SemiAnalysis