Hardware & Computing
Chip architecture, GPUs, quantum computing, custom silicon, memory-centric computing, semiconductor supply chains
Realizing Lattice Surgery on Two Distance-Three Repetition Codes with Superconducting Qubits
First experimental demonstration of lattice surgery on superconducting qubits — merges two distance-three repetition-code qubits using fault-tolerant circuits, validating a core building block for scaling surface codes
Deep Neural Network Inference on an Integrated, Reconfigurable Photonic Tensor Processor
First production-ready photonic tensor processor for DNN inference — packaged in a 19-inch rack unit, PyTorch-integrated, MNIST + CIFAR-10 benchmarked. Runs pretrained networks without chip-specific retraining
Integrated Photonic Neural Network with On-Chip Backpropagation Training
First integrated photonic deep neural network with end-to-end on-chip gradient-descent backpropagation — all linear AND nonlinear computations on a single silicon photonic chip. 92.5% accuracy on 2D classification; automatically compensates for fabrication variations
Memory Scarcity, Open Models, and the Restructuring of the AI Industry, 2026-2030
Quantitative scenario model showing the 2026 DRAM/HBM price surge creates a persistent entrant-incumbent inference-cost gap that never closes over 2026-2030 (3.2x in 2026, narrowing to ~1.9x in 2027, re-widening to 3-4x by 2029-30) via a depreciation-conveyor mechanism; five probability-weighted scenarios (Rotating Landlord Oligopoly 25%, Commoditization Crash 25%, Jevons Absorption 20%, System-Layer Re-differentiation 18%, Geopolitical Bifurcation 12%) map the resolution.
Quantum Error Correction Below the Surface Code Threshold
Google Willow: distance-5 and distance-7 surface codes operate below threshold — logical error suppression factor Λ = 2.14 per 2 distance steps; distance-7 achieves 0.143% error per cycle; logical memory exceeds physical qubit lifetime by 2.4x
From Tensor Buffer to Distributed Memory Hierarchy: A Survey of KV Cache Management for LLM Serving
First systematic taxonomy of 30+ KV-cache-management systems across four design dimensions (locality, lifetime, ownership, substrate) and five architectural patterns (local-paged, disaggregated-pipeline, shared-store, memory-pool, hybrid-tier); identifies seven evaluation-methodology gaps tied to fault tolerance, tiered eviction, speculative decoding, and MoE serving. Best current map of how the serving-software layer answers the memory-wall problem this topic already tracks at the hardware layer.
TokenStack: A Heterogeneous HBM-PIM Architecture and Runtime for Efficient LLM Inference
Concrete HBM4-logic-die PIM architecture: separates memory stacks into capacity-focused vs. compute-enabled layers, using the HBM4 base die as a local controller; claims 1.62x geomean token throughput, 1.70x latency-sensitive serving capacity, 30-47% per-token energy reduction on production-derived workloads. Directly answers two open Knowledge Gaps already flagged in this topic's frontier.md ('Commercial PIM product specs' and 'C-HBM4E NMC workload adoption'). Published 2026-05-07 — just outside the strict 60-day discovery window but flagged given the direct gap match.
StreamDQ: Near-Memory Weight DeQuantization in Custom HBM for Scalable AI Inference Acceleration
SK Hynix engineers put dequantization logic on the HBM base die (DeQuantization Blocks) so quantized weights are unpacked memory-side during standard loads, eliminating GPU CUDA-core dequantization. Up to 7.08x GEMM speedup, 90.23% lower energy, per-DQB 0.127mm2/0.355W in 12nm, 54.68% end-to-end LLM latency reduction and 2.20x decode throughput. First primary memory-maker technical source in this KB (architecture side).
AMMA: A Multi-Chiplet Memory-Centric Architecture for Low-Latency 1M Context Attention Serving
Removes the GPU from the center of long-context attention serving: replaces GPU compute dies with 16 HBM-PNM cubes (4x4 UCIe 3.0 mesh) in a multi-chiplet package -- 44 TB/s aggregate bandwidth / 240W package (vs H100 3.35 TB/s / 700W), 15.5x lower attention latency and 6.9x lower energy vs H100 on 1M-token decode attention (also 1.1-2.5x vs Rubin, 1.4-3.4x vs NeuPIMs). DSE finding: per-cube compute saturates ~96 TFLOPS then bandwidth-bound; comms-reordering speedup scales 2.7x->65.4x from 8K->1M sequence length. Names NVIDIA Rubin's GPU-LPU platform as the GPU-centric baseline it argues against. Boundary case (Apr 2026, outside 7-day window) ingested for direct chiplet + memory-centric gap match.
C2KV: Compressed and Composable KV Cache Reuse for Efficient LLM Inference
Software framework making the KV cache position-agnostic, compressible AND reusable at once via a lightweight sidecar Extractor learning a composable/compressed KV manifold, so non-prefix KV blocks concatenate and reuse without accuracy collapse. Compression ratio 4x primary (8x/16x also evaluated); up to 17x long-context inference speedup preserving quality; C2KV-4x accuracy beats even Full Recompute on MuSiQue (0.3587 vs 0.3198) and 2WikiMQA (0.4477 vs 0.4018); decode-time latency scaling flattened even at 128k tokens. Algorithm-layer complement to the near-memory KV hardware work.
Inside the NVIDIA Vera Rubin Platform
Six-chip co-designed AI supercomputer platform: 50 PFLOPS FP4 inference, 288GB HBM4 at 22TB/s, 5x improvement over Blackwell
Quantinuum Demonstrates Quantum Computations With 94 Protected Logical Qubits
94 error-protected logical qubits running 'beyond break-even' on a trapped-ion processor using 98 physical qubits — iceberg codes dramatically reduce encoding overhead
IBM Delivers New Quantum Processors, Software, and Algorithm Breakthroughs on Path to Advantage and Fault Tolerance
IBM Quantum Nighthawk (120 qubits, 5000 two-qubit gates) ships end of 2025 with concrete path: verified quantum advantage by end-2026, fault-tolerant system by 2029
Lightmatter: A New Kind of Computer — Photonic Processor Running Production Transformers
First photonic processor to run unmodified transformers + CNNs + RL at near-32-bit-float accuracy — no fine-tuning, no quantization-aware training. 65.5 TOPS (ABFP16) at 78W electrical + 1.6W optical, with 3D-integrated six-chip design using ~1M photonic components
NVIDIA, ASML, TSMC and Synopsys Set Foundation for Next-Generation Chip Manufacturing
NVIDIA cuLitho computational-lithography library deepens integration with ASML, TSMC, and Synopsys. GPU-accelerated mask synthesis becomes a structural enabler for sub-2nm production and a softener for TSMC's deferral of high-NA EUV
NVIDIA Vera Rubin Ramps Into Full Production to Power Agentic AI Factories Worldwide
NVIDIA confirms the Vera Rubin platform is ramping into full production (May 2026), production shipments begin fall 2026 across 350+ factories in 30 countries; 10x agent throughput at scale vs Grace Blackwell.
Expanding Our Use of Google Cloud TPUs and Services
Anthropic commits to ~1 million Google TPUs (Ironwood) and >1 GW capacity online in 2026 (tens of billions $); runs a three-platform strategy (TPUs + AWS Trainium + NVIDIA GPUs). Demand-side anchor for the custom-silicon inflection.
TSMC — 6-K: June 2026 Revenue Report (filed 2026-07-13)
June 2026 consolidated revenue NT$442.68B (+6.2% MoM, +67.9% YoY); H1 2026 revenue NT$2,404.48B (+35.6% YoY).
TSMC — Q2 2026 Earnings Release + Quarterly Management Report
Full Q2'26 print (primary, TSMC IR): GM 67.7% above the 65.5-67.5% guided ceiling, OpM 60.3%, revenue US$40.20B/NT$1,270.38B at top of guidance, HPC 66% (60->61->66 progression), Q2 capex US$15.70B/H1 US$26.80B, 2nm 3% of wafer revenue with N2-ramp dilution active.
ASML — Q2 2026 Financial Results
Q2'26 beat (EUR9.33B net sales / 54.0% GM, both above guidance) + FY26 guidance raise to EUR43-45B/54-56% GM (+20.5% midpoint since the Feb 20-F). Beat engine was Installed-Base/service upside (+EUR300M), not new systems.
Intel Q2 2026 Results (Actual Print) — 8-K Ex-99.1
ACTUAL Q2 2026: revenue $16,128M (+25% YoY, seventh straight guide-beat); GAAP EPS $(2.16) is entirely a $12,529M non-cash CHIPS Act Escrowed-Shares mark, non-GAAP EPS $0.42 and GAAP operating income POSITIVE $1,796M; Foundry loss narrowed to $(2,089)M/(36.2)% (first simultaneous margin+dollar improvement); gross capex FELL 41% YoY to $2,652M (the deeply negative Adjusted FCF is an Apollo/Fab 34 JV buyout, not capex). Panther Lake in HVM on ASML High-NA EUV. No FY26 capex-dollar guide; 18A yield still undisclosed.
Prefill/Decode-Aware Evaluation of LLM Inference on Emerging AI Accelerators
Empirical head-to-head of GPUs vs. GroqRack across the prefill (compute-bound) / decode (memory-bound) split using Llama2-7B: GPUs consistently win prefill, GroqRack wins decode TPOT at small batch, GPU decode advantage returns at large batch. Grounds 'which architecture wins which inference phase' in independent (Argonne) benchmarks rather than vendor claims — relevant to both this topic's rack-scale-compute frontier and inference-economics cost-per-phase modeling.
Custom Silicon Inflection 2026: Hyperscaler ASICs vs NVIDIA GPU
Deep technical analysis arguing NVIDIA's rack-as-product co-design strategy deepens lock-in despite custom ASIC growth at 44.6% CAGR
The Angstrom Era Arrives: TSMC Enters 2nm Mass Production and Unveils 1.6nm Roadmap
TSMC N2 hit mass production Q4 2025 (65-75% yield, Apple got >50% of capacity); A16 (1.6nm) with backside-power Super Power Rail targets late 2026 volume — first departure from FinFET in a decade
HBM Architectural Shakeup: HBM4, HBM4E, C-HBM4E — 3nm Base Dies Enable 2.5x Performance
HBM base dies move from DRAM to 3nm logic (TSMC N3P) — enables 2.5x bandwidth (3 TB/s per stack), 2x channels, C-HBM4E adds custom base dies with near-memory compute
Memory-Centric Computing: A Paradigm Shift for Sustainable and Efficient Systems
Argues processor-centric computing is fundamentally broken: 60–90% of system energy is data movement, not compute; DRAM can compute (RowClone, Ambit); reliability threats (RowHammer, RowPress, column disturbance) force memory intelligence anyway; JEDEC + trillion-dollar incumbency is the bottleneck, not technology
TSMC to Quadruple Advanced Packaging Capacity: Reaching 130,000 CoWoS Wafers Monthly by Late 2026
TSMC CoWoS ramp: ~35K wafers/mo (late 2024) → 75K (end 2025) → 130K target (end 2026); NVIDIA secures ~60% of capacity.
SK hynix 2026 Outlook: HBM3E Dominates, HBM4 Dual Strategy Amid 3 Market Headwinds
HBM3E 12-Hi 36GB ≈ 2/3 of 2026 HBM shipments; HBM4 16-Hi 48GB targets Q4 2026; SK Hynix ~60% share, 2026 capacity pre-booked by NVIDIA + OpenAI.
U.S. AI Data Center Delays: 7 GW Capacity Crisis (2026)
12 GW announced 2026 vs 5 GW under construction = 7 GW shortfall; AI DC load ~10 GW by end-2026; AEP queue 190 GW raw / 24 GW committed.
Global AI Server Shipments Forecast to Grow Over 28% YoY in 2026, with a Rising Share of ASIC-Based Systems
TrendForce: 2026 AI server shipments +28% YoY; ASIC-based systems reach 27.8% of shipments (highest since 2023), GPUs 69.7%; top-5 NA CSP capex +40% YoY; Google TPUs sold externally (Anthropic).
The Custom AI ASIC State of Play (May 2026) — Broadcom Deals, Google TPUs, Meta MTIA & Beyond
May-2026 ASIC state-of-play: Broadcom ~60% / Marvell ~35% of the custom-AI-ASIC co-design market; Marvell ~$11B AI ASIC revenue 2026; programs — TPU v7 Ironwood (4,614 FP8 TFLOPS, 192GB HBM3E, 7.37 TB/s), Maia 200, Trainium3 (Q2 2026), MTIA, OpenAI Titan.
Close read: Vintage Breakeven (§6) and the Demand-Measurement Critique (§9.1/§9.3) — Matsuoka 2607.07207
Primary-text close read of the full 22-page PDF. Corrects the parent ingest on four points: author is RIKEN R-CCS not independent; vintage breakeven is a 16-cell grid (4 vintages x 2 regimes x 2 HBM branches) not 3 rows; the 2026 vintage's regime exposure was INVERTED (worse under sticky ~31.3%, not coupled ~24.5%); custom-silicon build cost is $0.082/PB not $0.072. AUTHORITATIVE wherever it differs from the parent.
TSMC CoWoS Supply-Demand Gap Reportedly Narrowing from 20% to 10% by End-2026 as Capacity Expands
June-2026 CoWoS refresh (projection, as-of 2026-06-15): TSMC monthly capacity 120K-140K wafers by end-2026 (industry ~200K incl. 50-60K OSAT); supply-demand gap narrowing ~20% to ~10% by end-2026, shortage moderating in 2027; >60% TSMC expansion by 2027, CAGR >80% 2022-27; CoPoS pilots mid-2027, MP 2028-29 with NVIDIA Feynman first customer.
Google Expands Quantum Efforts to Include Neutral Atom Systems
Google Quantum AI adopts a dual-modality strategy — adds neutral atom computing alongside Willow superconducting, via strategic investment in QuEra. Internal effort led by Adam Kaufman (CU Boulder). Signals that neutral atoms are now a peer architecture, not a challenger
TSMC Debuts A13 Technology at 2026 North America Technology Symposium
TSMC unveils A13 (1.3nm direct shrink of A14) and N2U process nodes at NA Tech Symposium — A13 production targeted for 2029 for AI/HPC, N2U a more affordable variant for phones/laptops/AI; Arizona advanced packaging facility announced
TSMC Delays Use of ASML's High-NA EUV Machines Over Cost Concerns
TSMC publicly defers high-NA EUV adoption until at least 2029, citing ~$400M per-machine cost (vs ~$200M for current EUV). Plans to squeeze more performance from existing EUV through process optimization (A13, N2U) — major signal for ASML revenue
NVIDIA Snaps Up AI Chip Packaging Capacity as TSMC Expands in U.S.
NVIDIA has reserved the majority of TSMC's most advanced packaging capacity (CoWoS), making advanced packaging — not fabrication — the next bottleneck for AI accelerator supply