Nanosheet GAA Transistor

The move from FinFET to Nanosheet Gate-All-Around (GAAFET) transistors is the first architectural shift in over a decade of semiconductor manufacturing. In FinFET, the gate wraps three sides of a silicon fin; in GAAFET, the gate fully surrounds the channel on all four sides, giving superior electrostatic control and reducing current leakage. TSMC's N2 (2nm) node entered mass production in Q4 2025 with healthy 65–75% yields and Apple absorbing over 50% of initial capacity.

The follow-on node, A16 (1.6nm) in late 2026, introduces Super Power Rail — a backside power delivery system that moves the power network to the wafer rear, eliminates nano-Through-Silicon-Vias, and dedicates the front side exclusively for signal routing. This is more aggressive than Intel's PowerVia on 18A and unlocks an 8–10% speed boost plus 20% power efficiency over N2P.

The economic consequence is bifurcation. A16 wafers at $45–50k each push the node into hyperscaler + flagship-only territory — Apple (A20 for iPhone 18), NVIDIA (Feynman GPU), and hyperscaler custom ASICs (Broadcom/Marvell designs for Microsoft, Alphabet, Meta). Everything else stays on N3/N2 for years.

Key Claims

• N2 in mass production Q4 2025 — TSMC confirmed during Q4 earnings. Evidence: strong (TSMC Angstrom Era)
• 65–75% N2 yield — ahead of Samsung and Intel. Evidence: strong (TSMC Angstrom Era)
• Apple took >50% of initial N2 capacity — for A20 in iPhone 18. Evidence: strong (TSMC Angstrom Era)
• 10–15% speed improvement at same power vs N3E — Evidence: strong (TSMC Angstrom Era)
• 25–30% power reduction at same clock vs N3E — Evidence: strong (TSMC Angstrom Era)
• A16 with Super Power Rail targets late 2026 volume — backside power delivery eliminates nano-TSVs. Evidence: strong (TSMC Angstrom Era)
• A16: 8–10% speed, 20% power efficiency over N2P — Evidence: moderate (TSMC Angstrom Era)
• NVIDIA Feynman GPU targets A16 — Evidence: strong (TSMC Angstrom Era)
• Wafer cost $45–50k at A16 — creates hyperscaler-only economics. Evidence: moderate (TSMC Angstrom Era)

N2 vs N3E Performance

A16 vs N2P

Key Customers

Open Questions

• Does Samsung's GAA at 3nm catch up, or does TSMC extend its lead into the angstrom era?
• What does the $45–50k A16 wafer cost mean for non-hyperscaler customers?
• Can US fabs (Arizona) deliver A16 on a comparable timeline to Taiwan, or does geopolitical concentration persist?
• How does High-NA EUV investment for A14 (~2027–2028) change the economics?
• Does NVIDIA Feynman on A16 open more headroom than HBM4E alone?

Related Concepts

• HBM4 Memory Architecture — HBM4 base dies move to TSMC logic processes (N3P); A16 logic pairs with HBM4E memory
• Custom Silicon vs GPU — A16 is the substrate for both NVIDIA Feynman and hyperscaler ASICs
• Rack-Scale AI Compute — A16 logic + HBM4E + CoWoS-L is the substrate for post-Rubin racks

Backlinks

Pages that reference this concept:

• TSMC Angstrom Era
• TSMC

Changelog

• 2026-04-17 — Initial compilation from TSMC Angstrom Era analysis.