SK Hynix

Type: Company (DRAM / HBM manufacturer, Icheon, South Korea)

SK Hynix is the HBM share leader and therefore one of the two or three hands on the throttle of AI accelerator supply. It matters to this KB in two distinct ways: as the supply-side gate on how many accelerators can be built at all, and as the price-setter on the input that constitutes 40–50% of an accelerator's bill of materials — the term that drives every inference-cost model on Memory Scarcity & Inference Economics.

Confidence: low, and deliberately so — but now with one important qualification. The supply/pricing picture on this page still rests on a January 2026 third-party outlook plus figures cited second-hand inside a preprint: there is no primary SK Hynix filing, earnings release, or investor material in this KB. Treat all supply, ASP, capacity and allocation numbers below as the entry state of 2026 pending the print.

What did change (2026-07-23): the KB now holds its first primary SK Hynix technical source — StreamDQ (arXiv:2607.08993), a paper authored entirely by SK Hynix engineers (Icheon). That closes the memory-maker gap on the architecture / near-memory axis (what SK Hynix intends to build into a custom-HBM base die). It does nothing for the supply/pricing axis, which is the load-bearing one for this page. Hold the two apart.

SK Hynix reports 2026-07-29. Samsung reports 2026-07-30. Both dates verified against primary filings this week. Those prints supersede the supply/pricing state below. (Ignore any secondary source claiming Samsung printed 2026-07-23 — the desk-verified Samsung date is 07-30.)

Position (as of the January 2026 outlook — now six months stale)

The strategically important line is the mix: the generation shipping the volume in 2026 is HBM3E, not HBM4. HBM4's headline bandwidth numbers describe the leading edge of the roadmap, not the majority of units sold.

Why the pre-booking matters more than the share

If 2026 HBM capacity is pre-booked by NVIDIA and OpenAI, then new entrants are supply-gated until 2027 regardless of design merit. That is the supply-side counterpart to the demand-side finding on the memory-scarcity page: a custom accelerator program removes merchant GPU margin but not the memory premium, because HBM is priced by the same three suppliers under the same shortage no matter who owns the logic die. Access, not architecture, is the scarce thing — see Custom Silicon vs GPU.

Processing-in-memory work

SK Hynix is one of the few memory makers with shipped PIM silicon rather than slideware: the AiMX card (32 GB, GDDR6-AiM) ran Llama 2 70B at Hot Chips 2024 / AI HW Summit 2024, operating at 1.25 V vs 1.35 V standard for roughly 80% data-movement power reduction. Watch for an LPDDR6-AiM variant aimed at on-device AI. See Processing-In-Memory.

StreamDQ — the memory maker bids to put compute on the base die (Jul 2026)

This is the single most important thing to know about SK Hynix's posture, and it is new. In StreamDQ (arXiv:2607.08993, 9 Jul 2026), SK Hynix engineers describe putting dequantization logic on the HBM base die — compact DeQuantization Blocks (DQBs) that unpack quantized weights (INT4/INT8/FP8 → FP16/BF16) inline on standard memory loads, one DQB per pseudo-channel controller, selected by a 3-bit sideband tag, with no GPU ISA change. The GPU's CUDA-core dequantization step is bypassed entirely. Reported (the authors' own simulated/synthesized results): up to 7.08× GEMM speedup, 90.23% lower energy, 54.68% end-to-end LLM latency reduction, 2.20× decode throughput; per-DQB 0.127 mm² / 0.355 W in a 12 nm process, 11.36 W per stack across 32 DQBs.

Why it reframes SK Hynix's role. For fifty years the memory maker sold a passive component: the base die stored and returned bytes, and all arithmetic happened on the processor. StreamDQ is SK Hynix — the party that actually fabricates the stack — on record that the base die should compute. It is the KB's first primary memory-maker technical source on any subject, and it says the memory maker intends to bid for a slice of the compute, not just supply the capacity.

The architecture-vs-supply distinction — hold it precisely. StreamDQ is a technical/architecture paper. It tells you what SK Hynix wants to build into a custom-HBM base die. It tells you nothing about what SK Hynix will charge, how much it can make, or who has booked it — the supply/ASP/capacity/allocation picture that gates how many accelerators exist and at what memory premium. That picture remains a stale January outlook plus second-hand TrendForce figures, and it resolves (or doesn't) at the 2026-07-29 print. Do not let a strong architecture signal be read as a supply signal; they are different axes, and only one of them just improved.

And it is not a product. StreamDQ is a research preprint with simulated results, not a shipping part with a spec sheet or a committed custom-HBM base-die roadmap. Its own advantage shrinks at large batch (where dequant is a small fraction of runtime). Treat it as intent-plus-feasibility, not a delivered capability.

Key Contributions

• ~60% HBM market share; HBM3E 12-Hi 36GB ≈ 2/3 of 2026 HBM shipments; HBM4 16-Hi 48GB targeted Q4 2026. Evidence: moderate — January-2026 third-party outlook, now stale; raw ingest is a search-snippet summary (WebFetch blocked) (SK hynix outlook)
• 2026 HBM capacity reported pre-booked by NVIDIA + OpenAI, gating new entrants until 2027. Evidence: moderate — same source, no primary confirmation (SK hynix outlook)
• AiMX (GDDR6-AiM) ran Llama 2 70B with ~80% data-movement power reduction. Evidence: strong — SK Hynix technical disclosure at Hot Chips 2024 (Mutlu synthesis)
• HBM base dies moved to TSMC logic processes, restructuring the supplier relationship — the DRAM maker no longer controls the whole stack. Evidence: strong (HBM4 Shakeup)
• StreamDQ: near-memory weight dequantization on the HBM base die (DeQuantization Blocks, INT4/INT8/FP8→FP16/BF16, 3-bit sideband tag, no GPU ISA change) — up to 7.08× GEMM, 90.23% lower energy, 54.68% end-to-end latency; 0.127 mm² / 0.355 W per DQB in 12 nm. The KB's first primary SK Hynix technical source. Evidence: moderate — SK Hynix preprint, authors' own simulated results, not a shipping product; architecture axis only, says nothing about supply/pricing (StreamDQ)

What This KB Explicitly Does NOT Know

StreamDQ does not help here. It is a primary SK Hynix source, but on the architecture axis only — it says what the base die should compute, not what the company will supply, charge, or allocate. Every item below is a supply/commercial gap, and StreamDQ fills none of them.

The memory-scarcity preprint that supplies this KB's pricing framework contains no supplier-level analysis whatsoever — no per-supplier capex, allocation, margin, or strategy. It models memory scarcity as a single exogenous input. It therefore cannot corroborate any SK Hynix-specific claim, and should never be cited as a source for one. Missing here, all of it primary-source work:

• Capex, capacity by node, and HBM vs commodity-DRAM wafer allocation
• Margin trajectory and HBM ASP
• Customer concentration and contract structure (are the "pre-bookings" LTAs or intent?)
• HBM4 qualification status with each accelerator customer
• Competitive position vs Samsung and Micron on HBM4 16-Hi

Mentioned In

• HBM4 Memory Architecture — 2026 supply mix
• Memory Scarcity & Inference Economics — one of the three suppliers pricing the premium
• Processing-In-Memory — AiM / AiMX
• Advanced Packaging & CoWoS Capacity — the other capacity gate

Related Entities

• TSMC — manufactures the HBM4 logic base dies SK Hynix stacks onto
• NVIDIA — the anchor customer reported to have pre-booked 2026 capacity

Changelog

• 2026-07-23 — Added StreamDQ (arXiv:2607.08993), the KB's first primary SK Hynix technical source: near-memory weight dequantization on the HBM base die. Reframed the entity — the memory maker is now on record bidding to put compute on the base die, not just supply capacity ("memory stops being a passive component"). Recorded the architecture-vs-supply distinction as the load-bearing caveat: StreamDQ closes the memory-maker gap on the near-memory/architecture axis but does nothing for supply/ASP/capacity/allocation, which the 2026-07-29 print addresses. Kept confidence: low because the supply/pricing picture — the load-bearing one for this page — is unchanged. Flagged StreamDQ as a simulated preprint, not a product. Reconfirmed desk-verified print dates (SK Hynix 07-29, Samsung 07-30). +1 source.
• 2026-07-22 — Page created during the incremental compile. Fills a LENS-required named entity that the KB had been missing entirely despite HBM being load-bearing across the topic. Confidence set low and an explicit "what we don't know" section added, because no primary SK Hynix source exists in this KB — the 2026-07-29 print is the first opportunity to fix that.