Rung 06 / Model graph to silicon

Compilers & Kernels

The layer between a model graph and the silicon.

2
Sources
Paper1Report1AnalysisNews

In scope: CUDA and Triton, kernel fusion and autotuning, compiler stacks (XLA, TVM, Inductor), custom kernels for attention and quantization, portability across accelerators. Out: the serving system above it (serving), the chip below it (hardware).

Five loose operators entering a taper and leaving as one fused copper solid.
CUDATritonKernel fusionPortability

No sources yet. This rung is open and scoped, but nothing has been read into it — no papers registered, no concepts compiled. It will fill from the top of the reading queue rather than from a summary of other people’s summaries.

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