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Rung 07 Compilers & KernelsSwitch rung
Rung 07 / Model graph to silicon

Compilers & Kernels

The layer between a model graph and the silicon.

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A steel press die with a copper blank beneath it, on paper.

In scope: CUDA and Triton, kernel fusion and autotuning, compiler stacks (XLA, TVM, Inductor), custom kernels for attention and quantization, portability across accelerators. Out: the serving system above it (serving), the chip below it (hardware).

Five loose operators entering a taper and leaving as one fused copper solid.
CUDATritonKernel fusionPortability
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01FP4 Reasoning Quantizationearly02Kernel Portability Across Chip Generationsactive03Launch Overhead: Why a Faster GPU Doesn't Speed Up One Useractive04The Non-Matmul Bottleneckactive05Quantized KV Cache: Stored Small, Computed Largeactive