Hardware & Computing — Timeline

Timeline

2024

August 2024

  • Aug 24 — Google Willow below surface-code threshold (Acharya et al., arXiv 2408.13687). Distance-5 and distance-7 surface codes suppress logical errors exponentially (Λ=2.14 per 2 distance steps). d=7 code at 0.143% error per cycle on 101 qubits. Logical memory 2.4× physical lifetime. Real-time decoding at d=5 over 1M cycles. (Willow)

2025

April 2025

  • Apr 9 — Lightmatter A New Kind of Computer. First photonic processor to run unmodified BERT + ResNet + Atari RL at near-FP32 accuracy. 65.5 TOPS at 78W electrical + 1.6W optical. 1M photonic components, 6 chips 3D-integrated. (Lightmatter)

Q4 2025

  • Oct — Google acquires Atlantic Quantum (fluxonium-based superconducting qubits) — expands Willow roadmap. (Google+QuEra context)
  • Oct 23 — Anthropic commits to ~1M Google TPUs (Ironwood) + >1 GW capacity online in 2026. Tens of billions of dollars; three-platform strategy (TPUs + AWS Trainium + NVIDIA GPUs). The demand-side anchor for the custom-silicon inflection. (Anthropic)
  • Nov 12 — IBM Quantum Nighthawk + Loon announced. 120 qubits, 5,000 two-qubit gates at launch, 218 tunable couplers. qLDPC real-time decoding in <480ns (10× prior art). Roadmap: verified quantum advantage end-2026, fault tolerance by 2029. (IBM)
  • Dec 2 — HBM4 architectural shakeup (Tom's Hardware, TSMC + GUC). Base dies move from DRAM to TSMC 12FFC / N5 / N3P. HBM4E 2.5× bandwidth vs HBM3E (3 TB/s per stack). C-HBM4E introduces custom base dies with near-memory compute. (HBM4 Shakeup)
  • Q4 2025 — TSMC N2 (2nm) mass production begins. 65-75% yield. Apple takes >50% of initial capacity for A20 (iPhone 18). First Nanosheet GAA node in volume. (TSMC Angstrom Era)
  • End 2025 — IBM Nighthawk delivery.
  • 2025 — Pasqal demonstrates 2 logical qubits on neutral-atom platform (European first). (Google+QuEra)
  • 2025 — QuEra delivers error-correction-ready machine to AIST Japan. (Google+QuEra)

2026

January 2026

  • Jan 5 — SK hynix 2026 HBM outlook (TrendForce). HBM3E 12-Hi 36GB set to carry ~2/3 of 2026 HBM shipments; HBM4 16-Hi 48GB production targeted Q4 2026; SK Hynix ~60% share with 2026 capacity reportedly pre-booked by NVIDIA + OpenAI. The entry state of 2026 — six months stale as of this compile; superseded by the 2026-07-29 print. (SK hynix outlook)
  • Jan 5 — NVIDIA Vera Rubin announced at CES. 6 co-designed chips. 50 PFLOPS FP4 per GPU, 288 GB HBM4 at 22 TB/s, NVLink 6 at 3.6 TB/s. (NVIDIA)
  • Jan 8 — Besedin et al. lattice surgery on superconducting qubits posted to arXiv (2501.04612). First superconducting lattice surgery demonstration — two distance-3 repetition-code qubits via fault-tolerant circuits. Published in Nature Physics (Vol 22(2), pp 189-194). (Besedin)
  • Jan 15 — Photonic tensor processor (imec, Nature Commns). 19-inch rack unit with PyTorch integration. iSiPP50G silicon photonics platform. 9×3 all-optical crossbar. Pretrained networks run without chip-specific retraining. MNIST + CIFAR-10 benchmarks. (PTP)
  • Jan 20 — TrendForce 2026 AI server forecast. Shipments +28% YoY; ASIC-based systems reach 27.8% of shipments (highest since 2023), GPUs 69.7%; top-5 NA CSP capex +40% YoY. First year ASIC growth (44.6%) outpaces merchant GPU (16.1%). (TrendForce)
  • Jan 21 — TSMC A16 roadmap unveiled. 1.6nm with Super Power Rail (backside power). Late 2026 volume production. NVIDIA Feynman flagship customer. Wafer cost ~$45-50k. (TSMC)

February 2026

  • Feb 5 — TSMC CoWoS quadrupling plan reported. Advanced-packaging capacity ~35K wafers/mo (late 2024) → ~75K (end 2025) → 120–130K target (end 2026); AP6 Zhunan / AP7 Chiayi / AP8 Tainan; NVIDIA reported at ~60% of capacity; CoWoS-L/S fully booked through 2026. Target, not realized output; summary-derived source. (CoWoS ramp)
  • Feb 25 — SemiAnalysis co-design analysis. Custom ASICs 44.6% CAGR vs GPU 16.1%. NVIDIA inference share projected 20-30% by 2028. (SemiAnalysis)

March 2026

  • Mar 20 — Ashtiani et al. on-chip photonic backprop (Nature). First integrated photonic DNN with end-to-end on-chip gradient-descent training. 92.5% on 2D classification matching digital reference. Opto-electronic gradient schemes (Nokia Bell Labs). (Ashtiani)
  • Mar 26 — Quantinuum 94 logical qubits beyond break-even. Iceberg codes on 98 physical qubits. Logical gate error ~1e-4; 95% GHZ fidelity. (Quantinuum)
  • Vera Rubin POD announced — 7th chip, extended rack-scale config. (NVIDIA)
  • Q1 2026 — US AI data-center power shortfall quantified. 12 GW of new demand announced for 2026 completion vs ~5 GW under active construction = 7 GW gap; only ~1/3 of announced 2026 sites had broken ground. AEP: 24 GW committed by 2030 against a 190 GW raw interconnect queue; CenterPoint large-load requests 1 GW → 8 GW in one year. Relief expected 2027–28. Weak provenance — summary-derived ingest. (7 GW shortfall)

April 2026

  • Apr 6 — Anthropic expands Google/Broadcom compute deal — additional multi-gigawatt (~5 GW) next-generation TPU capacity starting 2027, on top of the 2026 1M-TPU commitment. (Anthropic)
  • Apr 3 — Google expands quantum efforts to neutral atom (HPCwire). Dual-modality strategy — adds neutral atom alongside Willow superconducting via strategic investment in QuEra. Internal program led by Adam Kaufman (CU Boulder). Three research pillars: QEC, Modeling & Simulation, Hardware. (Google+QuEra)
  • Apr 8 — NVIDIA reserves majority of TSMC advanced packaging (CoWoS) capacity (CNBC). Advanced packaging is now the binding constraint on AI accelerator supply — not fabrication. AMD, Broadcom, hyperscaler ASICs queue behind. (NVIDIA-TSMC packaging)
  • Apr 22 — TSMC publicly defers high-NA EUV adoption (Bloomberg). Kevin Zhang (TSMC Deputy COO): no current plans to adopt ASML's ~$400M-per-tool high-NA EUV. Plans to squeeze more from existing EUV via A13/N2U process optimization. Major negative read-through to ASML high-NA bookings. (TSMC EUV deferral)
  • Apr 23 — TSMC unveils A13 + N2U at NA Tech Symposium. A13 = direct shrink of A14, ~1.3nm class, 2029 production targeted for AI/HPC. N2U = cost-down N2 variant for phones/laptops/mid-tier AI. New advanced-packaging fab announced for Arizona. (TSMC A13/N2U)
  • Apr 23 — NVIDIA-ASML-TSMC-Synopsys cuLitho expansion. GPU-accelerated computational lithography integrated across the foundry-tooling stack. Softens the cost of TSMC's high-NA EUV deferral by extending what current EUV can deliver. NVIDIA's CUDA-style moat now spans mask synthesis. (cuLitho)
  • Apr 28 — AMMA preprint (arXiv:2604.26103). A multi-chiplet, memory-centric architecture that removes the GPU compute die from decode attention entirely, replacing it with HBM-PNM cubes (~2× memory bandwidth). Reports 15.5× lower attention latency and 6.9× lower energy vs H100 on 1M-token-context decode attention; names NVIDIA Rubin's GPU-LPU platform as the GPU-centric baseline it argues against. Academic preprint, simulated vs an H100 baseline; ingested 2026-07-23 as a boundary case filling the chiplet + memory-centric gaps. (AMMA)

May 2026

  • May 7 — TokenStack preprint (arXiv:2605.05639). Heterogeneous HBM-PIM architecture using the HBM4 logic base die as a stack-local controller, splitting stacks into dense capacity layers and PIM compute layers to keep hot KV near near-memory compute. Claims 1.62× geomean token throughput, 1.70× SLO-compliant capacity, 30–47% lower per-token energy vs AttAcc. Academic architecture, abstract-level in this KB. (arXiv)
  • May 26 — Custom AI ASIC state-of-play (Tom's Hardware). Broadcom ~60% / Marvell ~35% of the custom-AI-ASIC co-design market; Marvell ~$11B projected 2026 ASIC revenue. Named programs: Google Ironwood (4,614 FP8 TFLOPS, 192 GB HBM3E), Microsoft Maia 200, AWS Trainium3 (ramps Q2 2026), Meta MTIA, OpenAI Titan. (Custom AI ASIC state of play)
  • May 31 — NVIDIA Vera Rubin ramps into full production. Shipments begin fall 2026 across 350+ factories / 30 countries; "AI factory engine," 10x agent throughput at scale vs Grace Blackwell. (NVIDIA full-production)
  • 2026 (GTC) — Rubin CPX cancelled. The discrete long-context inference GPU (30 PFLOPS NVFP4, 128 GB GDDR7), roadmapped Sept 2025, is pulled. Rubin Ultra (2027, ~100 PFLOPS FP4, ~1 TB HBM4E) remains. (NVIDIA full-production)

June 2026

  • Jun 15 — TSMC CoWoS supply-demand refresh (TrendForce, as-of 2026-06-15). The flat 130K end-2026 target becomes a 120–140K/mo band; adding ~50–60K OSAT, combined industry approaches ~200K/mo; the supply-demand gap is projected to narrow ~20% → ~10% by end-2026, with the 2.5D shortage "moderating" in 2027 (>60% TSMC expansion by 2027, CAGR >80% 2022–27). Introduces CoPoS (panel-level successor): materials qualified Jun-2026, pilot mid-2027, MP 2028–29, NVIDIA Feynman first customer. Analysis-tier projection, not realized output. (CoWoS Jun-2026 refresh)
  • Jun 14 — Prefill/decode-aware accelerator evaluation (arXiv:2606.17104, HPAI4S'26 @ IEEE IPDPS 2026). First independent, non-vendor, phase-separated GPU-vs-non-GPU benchmark in this KB. On Llama2-7B: GPUs consistently win compute-bound prefill; GroqRack achieves significantly lower TPOT in memory-bound decode (batching unsupported); GPUs regain decode throughput advantage as batch size grows. Directional only — full text not ingested, no magnitudes recorded. (arXiv)
  • Jun 30 — KV cache management survey (arXiv:2607.02574). 30+ KV-management systems classified on four axes (locality, lifetime, ownership, substrate) collapsing into five archetypes (local-paged, disaggregated-pipeline, shared-store, memory-pool, hybrid-tier). Finds ownership explains much of the remaining design variance once workload and hardware are fixed; audits evaluations and names seven missing KV-specific measurements. (arXiv)

July 2026

  • Jul 8 — Matsuoka, "Memory Scarcity, Open Models, and the Restructuring of the AI Industry, 2026–2030" (arXiv:2607.07207, econ.GN). Single-author, non-peer-reviewed preprint from RIKEN R-CCS. Introduces $/PB (dollars per petabyte of bandwidth delivered) as the cost unit for bandwidth-bound decode; the depreciation conveyor keeping the entrant/incumbent gap open (3.2× 2026 → 1.9× 2027 → 3–4× 2029–30); a 16-cell vintage-breakeven grid; a five-bias demand-measurement critique; and five weighted scenarios. (Matsuoka)
  • Jul 9 — StreamDQ preprint (arXiv:2607.08993) — SK Hynix. SK Hynix engineers (Icheon) put dequantization logic on the HBM base die (DeQuantization Blocks): INT4/INT8/FP8 → FP16/BF16 unpacked inline on standard loads, one DQB per pseudo-channel controller, 3-bit sideband tag, no GPU ISA change. Reports up to 7.08× GEMM speedup, 90.23% lower energy, 54.68% end-to-end latency reduction, 2.20× decode throughput; 0.127 mm² / 0.355 W per DQB in 12 nm. The KB's first primary memory-maker technical source — the maker on record bidding to put compute on the base die. Preprint with simulated results, not a shipping product; architecture axis, not supply/pricing. (StreamDQ)
  • Jul 13 — TSMC Form 6-K, June 2026 revenue. NT$442.68B (+6.2% MoM, +67.9% YoY); H1 2026 NT$2,404.48B (+35.6% YoY). (TSMC 6-K)
  • Jul 15 — ASML Q2 2026 results. €9.33B net sales / 54.0% GM, both above guidance; FY26 guide raised to €43–45B / 54–56% GM (+20.5% midpoint since the February 20-F). Beat was Installed-Base/service-led (+€300M), not new systems. (ASML Q2'26)
  • Jul 16 — TSMC Q2 2026 print. GM 67.7% above the 65.5–67.5% guided ceiling; OpM 60.3%; revenue US$40.20B at the top of guidance; HPC 66% of revenue (60→61→66); Q2 capex US$15.70B / H1 US$26.80B; 2nm at 3% of wafer revenue with N2-ramp dilution demonstrably active yet margin still expanding. (TSMC Q2'26)
  • Jul 20 — Desk close read of arXiv:2607.07207 (full 22-page PDF). Corrects the KB's first ingest on four points: author is RIKEN R-CCS, not independent; the vintage-breakeven result is a 16-cell grid (4 vintages × 2 regimes × 2 HBM branches), not 3 rows; the 2026 vintage's regime exposure was inverted (worse under sticky ~31.3%, not coupled ~24.5%); custom-silicon build cost is $0.082/PB, not $0.072. Also recovers the dollar-denomination correction, the §9.2 reallocation channel and the §9.3 projection-vintage problem, all missing from the first pass. (close read)
  • Jul 20 — C²KV preprint (arXiv:2607.17715). Software-layer attack on the KV object: a position-agnostic, composable + compressed KV manifold (learned via a lightweight sidecar Extractor on a frozen base model) makes non-prefix KV blocks reusable without accuracy collapse — up to 17× long-context inference speedup while preserving quality. Frames the real long-context bottleneck as KV storage/transfer cost, not just prefill compute. Complements the near-memory hardware work (TokenStack / AMMA / StreamDQ). Preprint, authors' own benchmarks, abstract-level. (C²KV)

Upcoming — dates verified against primary filings

  • Jul 29 — SK Hynix Q2 2026 earnings. First primary SK Hynix source for this KB; supersedes the January HBM outlook. (SK Hynix)
  • Jul 30 — Samsung Q2 2026 earnings.

H1 2026 (Projected)

  • Pasqal 250-qubit QPU for quantum advantage attempt. (Google+QuEra)

H2 2026 (Projected)

  • Vera Rubin systems shipping — NVL72 racks to customer data centers. 72 GPUs, 260 TB/s aggregate, 180-220 kW liquid-cooled. (NVIDIA)
  • TSMC A16 volume production begins. NVIDIA Feynman on A16. (TSMC)
  • IBM targets verified quantum advantage by end of 2026. (IBM)
  • Pasqal targets 10,000 qubits. (Google+QuEra)
  • QuEra global customer availability. (Google+QuEra)
Timeline — Hardware & Computing | KB | MenFem