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Hardware
The silicon rung of the inference stack, read memory-first.
Memory bandwidth of one H100 SXM's 80 GB of HBM3 — the wall the arithmetic waits behind

In scope: the memory hierarchy and the memory wall, HBM and DRAM scaling, bandwidth and capacity limits, processing-in-memory, accelerator and NPU architecture, advanced packaging, and interconnect including optical interconnect and co-packaged optics. Memory is the binding constraint of this cycle. Out of scope: photonic compute (computing in light, as distinct from communicating in light) and quantum computing — frontier science with no near-term effect on what a token costs — and consumer buying advice, which is an editorial beat rather than research.
Hardware Concepts: The 2026 Substrate
Rack-scale compute, HBM4, custom silicon, quantum error correction, photonics, and memory-centric computing
Hardware Concepts Sprint
Fast recall on CoWoS, HBM4E, Willow's Λ, Nanosheet GAA, iceberg codes, neutral atoms, and PIM
Hardware Companies & Labs
Match the compute, silicon, quantum, and photonic players to their 2026 signatures
Hardware Supply Chain: Commercial Facts
Drill 8 structural facts about the hardware supply chain for hardware.
Hardware Timeline: The Substrate Shifts
Order the milestones from Google Willow through Vera Rubin's full production
The Hardware Frontier: Quantum, Foundry & ASICs
Three quantum architectures, foundry economics, the custom-silicon inflection, and the Rubin roadmap
Hardware Speed Round
Quick-fire recall on the numbers and names of the 2026 compute stack
Sourcing Frontier AI Compute in 2026
Make the chip, packaging, memory, and power calls the evidence supports
NVIDIA Dossier: recent revenue
Estimate NVIDIA's revenue across the last quarter.
The Memory-Centric Inversion
Rank AMMA, Rubin, and H100 by package bandwidth then power — the memory-centric design inverts the usual bandwidth-vs-power tradeoff