Research Frontier: Optical Computing

What's genuinely new and where the field is heading.

Active Frontiers

1. CPO Deployment Wave (2026-2028) — Now Two Integration Topologies

Status: Rapid commercial progress — production-ready; commercialization moving to ASIC/packaging partnerships Key sources: Ayar Labs $500M, TSMC COUPE, OIF 3.2T, CPO Five Trends, Lightmatter M1000, Lightmatter–GUC Key players: Ayar Labs, Lightmatter, TSMC Photonics, OIF, GUC

The co-packaged optics deployment wave is the most commercially advanced frontier in the knowledge base. The infrastructure layer is locked in: OIF's 3.2T standard provides multi-vendor interoperability; TSMC COUPE enables any TSMC customer to adopt optical I/O via UCIe; Ayar Labs' $500M Nvidia-backed raise (March 2026) funds mass production of TeraPHY chiplets at 200+ Tbps/package — 5x Rubin GPU bandwidth.

The energy case is compelling and specific: Nvidia's own testing shows 30W → 9W link power in 1.6T networks switching from pluggable transceivers to CPO. Since data movement consumes 60% of data center energy, CPO is a cost story as much as a performance story. At the OIF's projected 10 million CPO ports by 2029, the aggregate energy savings are enormous.

Two integration topologies now compete (new June 2026). Alongside the chiplet model (TeraPHY-style optical engines beside the compute die, standardized via UCIe/COUPE), Lightmatter's Passage M-series introduces the active photonic interposer: the M1000 is a >4,000 mm² multi-reticle interposer carrying 114 Tbps total optical bandwidth across 256 fibers, with electro-optical I/O routable anywhere on its surface for the die complex stacked on top, plus the first on-package solid-state optical circuit switching. Commercialization is also shifting from standards to ASIC/packaging partnerships: Lightmatter–GUC (Jan 2026) co-designs Passage 3D CPO into GUC's ASIC + advanced-packaging flow for hyperscalers — the interconnect analogue of Ayar Labs → TSMC. The open architectural question is whether chiplet-CPO and active-interposer converge or diverge for hyperscale scale-up.

Timeline:

• 2026 — Early CPO adopters in AI training clusters; Ayar Labs production samples; Q.ANT NPU 2 shipping; Lightmatter–GUC commercial 3D-CPO path established
• 2027 — Broader 800G/1.6T adoption; TSMC COUPE ecosystem matures; Lightmatter Qualcomm partnership
• 2028 — Photonic interconnects standard for AI-scale networking; 6.4T and 12.8T CPO generations emerging

Open problems:

• Thermal management of photonic ICs co-packaged with high-power logic dies (critical production blocker)
• Optical alignment yield at micron-scale precision in volume manufacturing
• InP laser supply chain constraints limiting total deployment pace
• Cost premium vs. pluggable optics at scale
• Active photonic interposer (Lightmatter M-series) vs. chiplet-CPO (Ayar Labs / TSMC COUPE): which wins, and do they converge?

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2. On-Chip Training Crosses the Threshold (June 2026)

Status: First end-to-end on-chip backpropagation demonstrated — lab scale Key sources: On-Chip Backprop PNN, Photonic CNN Pre-trained In-Situ Key players: Nokia Bell Labs

The defining research result of this refresh. Nokia Bell Labs (Ashtiani, Idjadi, Kim — Nature 651, 927-932, 2026) demonstrated the first integrated photonic deep neural network trained end-to-end with on-chip gradient-descent backpropagation, with all linear and nonlinear computation — including the nonlinear activation and its gradient — performed on a single photonic chip. This retires one of the field's oldest framing assumptions: that photonic chips are inference accelerators that must be trained on an external digital computer.

Why it matters beyond the demo: training on the same chip that runs inference lets the learned weights absorb the chip's own fabrication imperfections, so accuracy stays robust (>90% on nonlinear classification, matching digital references) despite the device-to-device variation that has always degraded externally-trained photonic networks. It is more fundamental than digital-twin/SPSA fine-tuning (Ranjan et al.), which still computes the gradient digitally — here the gradient runs in the optical domain.

This sharpens an emerging design axis: reconfigurable, on-chip-trainable processors (Bell Labs) versus ultra-dense fixed-function inverse-designed accelerators (Sydney, ~400M params/mm², trained once into the geometry). Different workloads may favor different poles; whether the two can be combined is open.

Open problems:

• Does on-chip training scale beyond lab-scale networks?
• What is the energy cost of on-chip training under full SimPhony-style system-level accounting?
• Can on-chip backprop be combined with ultra-dense fixed-function accelerators, or are density and trainability fundamentally in tension?

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3. The DAC/ADC Bottleneck Problem

Status: System-level constraint identified April 2026 — still awaiting community response Key sources: Harnessing Photonics for Machine Intelligence Key players: UT Austin / ASU (SimPhony)

This is the field's most important methodological correction of 2026. The SimPhony cross-layer benchmarking framework (UT Austin, April 12, 2026) is the first rigorous system-level accounting of photonic AI systems — modeling the full datapath rather than isolated optical components. The finding: DAC/ADC conversion consistently outweighs laser power and optical compute energy as the primary energy consumer. The efficiency advantages cited in most photonic compute papers measure only the optical core, not the mandatory analog-digital interfaces that surround it.

Implications:

• MZI meshes fail on Transformers — Reconfiguring MZI phases at token-rate timescales is thermally and control-limited; these architectures assume static weights and are structurally incompatible with dynamic attention mechanisms
• Time-multiplexed crossbar is the competitive architecture — Avoids MZI reconfiguration, achieves A100-competitive position in system-level benchmarks, surpasses B200 on energy efficiency
• Precision ceiling ~8 bits — Beyond this, efficiency collapses; brute-force precision scaling is unsustainable
• Peripheral overheads often exceed optical compute energy — Prior efficiency claims need re-measurement under full system accounting

This finding is recent enough (April 2026) that industry responses and follow-on work are not yet in this KB.

Open problems:

• What minimum DAC/ADC resolution preserves model accuracy for LLM inference?
• Can photonic architectures native to Transformer attention avoid the reconfiguration problem?
• What compilation tools exist to map standard ML models onto photonic hardware with correct system-level cost estimation?

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4. Photonic Compute Hardware — Accuracy + Density Validated, Scale Not Yet

Status: Lab accuracy and density validated; wafer-scale manufacturing remains open Key sources: Inverse-Designed Nanophotonic NN (Nat. Comm.), Nanophotonic Neural Network Sydney, Large-Scale Photonic Accelerator Nature, Fully-Programmable Photonic Processor Key players: University of Sydney, Nokia Bell Labs, SJTU / TuringQ

Results through mid-2026 establish that photonic chips can achieve practical accuracy and extreme density on real tasks:

• University of Sydney (now peer-reviewed in Nature Communications): ~400 million trainable parameters/mm² via inverse-designed subwavelength voxels; ~89% MNIST / ~90% MedNIST on-chip (90-99% across 10,000+ biomedical images) at picosecond timescales
• Nature 2025: 16,000+ component photonic chip benchmarks faster than GPU on specific workloads — largest-scale photonic accelerator demonstrated
• SJTU / TuringQ: 498-component chip achieves 97% MNIST accuracy AND 100% NP-complete problem accuracy on same hardware (7.22-bit precision)

The programmability milestone from SJTU (one chip, no modification, optimization + inference) plus the Sydney density figure plus Bell Labs' on-chip training (Frontier 2) together retire the "single-purpose inference engine" framing — at least at lab scale.

What's not yet solved: manufacturing yield for 16,000+ component circuits; programming model for non-expert users; whether on-chip training scales; and system-level efficiency under rigorous SimPhony-style accounting.

Open problems:

• Manufacturing yield for 16K+ component photonic circuits at wafer scale
• Software and compiler stack for deploying standard ML frameworks onto photonic hardware
• Can photonic accelerators handle training or only inference? Answered (Frontier 2) — open follow-on is whether on-chip training scales past lab networks
• Fixed-function density (Sydney) vs. reconfigurable trainability (Bell Labs): the live design trade-off
• What does the 16K-component chip look like under SimPhony system-level accounting?

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5. Quantum Photonics Convergence

Status: Steady research progress; QKD most commercially mature Key sources: Quantum Photonics on a Chip Key players: PsiQuantum, Xanadu (not yet in KB), Ben-Gurion University

Quantum photonics shares silicon photonics manufacturing infrastructure with classical photonic computing but operates in a fundamentally different regime — single-photon manipulation rather than coherent-field computation. The review by Katiyi and Karabchevsky (2025) synthesizes state-of-the-art across platforms, sources, and detectors.

Key status:

• SNSPDs >90% efficiency — Best detectors available, but require cryogenic operation (deployment-limiting)
• Quantum dots β ≈ 98% — Near-unity photon coupling into waveguides; still probabilistic emission
• Silicon photonics = preferred QKD platform — CMOS manufacturing compatibility for scalable quantum communication
• Room-temperature alternatives gap — SPADs at 65%, Ge APDs at 5.27% at 80K; order-of-magnitude below SNSPD

The commercial bridge is quantum key distribution (QKD): silicon photonic chips for quantum-secure communication are the most near-term application, requiring lower qubit counts than general quantum computing and directly leveraging the integrated photonics manufacturing base being built for classical CPO.

Open problems:

• Room-temperature single-photon detectors at >90% efficiency (would transform deployment economics)
• Deterministic single-photon sources (all current implementations are probabilistic)
• Heterogeneous integration of III-V emitters with silicon photonics at wafer scale

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Recent Breakthroughs (Compiled 2026-06-24)

Knowledge Gaps

Areas where the KB needs more sources:

• Nvidia Spectrum-X / Quantum-X Photonics — Nvidia's own CPO silicon-photonics switch line (Spectrum-X Photonics cited at up to 409.6 Tb/s, 2H-2026) is the elephant not yet in the KB. Suggested search: "Nvidia Spectrum-X Photonics co-packaged optics 2026"
• Broadcom CPO (Tomahawk 6 / Davisson) — Broadcom is shipping 3rd-gen CPO (Tomahawk 6 – Davisson, 3.5x better power efficiency than pluggables) and developing 4th-gen; missing from entities. Suggested search: "Broadcom Tomahawk Davisson co-packaged optics 2026"
• Intel silicon photonics — Intel has significant photonic integration investment; no KB coverage yet. Suggested search: "Intel silicon photonics foundry 2026"
• Lightmatter Envise photonic compute chip — Lightmatter's compute (vs. interconnect) product has only press-release coverage; no technical details. Suggested search: "Lightmatter Envise photonic processor specifications"
• On-chip-backprop scaling + energy — Bell Labs proved on-chip training at lab scale (Frontier 2); the open follow-on is whether it scales and its cost under SimPhony accounting. Suggested search: "scalable on-chip photonic backpropagation training 2026"
• Software/compiler stack for photonic chips — How ML engineers map PyTorch/JAX models to photonic hardware; toolchains; no KB coverage. Note: the imec/silicon-photonic tensor processor with a PyTorch interface (Nat. Comm. 2026) is a candidate ingest. Suggested search: "photonic tensor processor PyTorch interface imec 2026"
• PsiQuantum / Xanadu quantum photonics — Major quantum photonics companies entirely absent from KB. Suggested search: "PsiQuantum silicon photonics 2026 progress"
• System-level benchmarks post-SimPhony — Community response to UT Austin's findings; follow-on benchmarking work not yet captured