Research Frontier: Optical Computing

What's genuinely new and where the field is heading.

Active Frontiers

1. CPO Deployment Wave (2026-2028)

Status: Rapid commercial progress — production-ready Key sources: Ayar Labs $500M, TSMC COUPE, OIF 3.2T, CPO Five Trends Key players: Ayar Labs, Lightmatter, TSMC Photonics, OIF

The co-packaged optics deployment wave is the most commercially advanced frontier in the knowledge base. The infrastructure layer is locked in: OIF's 3.2T standard provides multi-vendor interoperability; TSMC COUPE enables any TSMC customer to adopt optical I/O via UCIe; Ayar Labs' $500M Nvidia-backed raise (March 2026) funds mass production of TeraPHY chiplets at 200+ Tbps/package — 5x Rubin GPU bandwidth.

The energy case is compelling and specific: Nvidia's own testing shows 30W → 9W link power in 1.6T networks switching from pluggable transceivers to CPO. Since data movement consumes 60% of data center energy, CPO is a cost story as much as a performance story. At the OIF's projected 10 million CPO ports by 2029, the aggregate energy savings are enormous.

Timeline:

• 2026 — Early CPO adopters in AI training clusters; Ayar Labs production samples; Q.ANT NPU 2 shipping
• 2027 — Broader 800G/1.6T adoption; TSMC COUPE ecosystem matures; Lightmatter Qualcomm partnership
• 2028 — Photonic interconnects standard for AI-scale networking; 6.4T and 12.8T CPO generations emerging

Open problems:

• Thermal management of photonic ICs co-packaged with high-power logic dies (critical production blocker)
• Optical alignment yield at micron-scale precision in volume manufacturing
• InP laser supply chain constraints limiting total deployment pace
• Cost premium vs. pluggable optics at scale

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2. The DAC/ADC Bottleneck Problem

Status: Newly identified system-level constraint — April 2026 Key sources: Harnessing Photonics for Machine Intelligence Key players: UT Austin / ASU (SimPhony)

This is the field's most important methodological correction of 2026. The SimPhony cross-layer benchmarking framework (UT Austin, April 12, 2026) is the first rigorous system-level accounting of photonic AI systems — modeling the full datapath rather than isolated optical components. The finding: DAC/ADC conversion consistently outweighs laser power and optical compute energy as the primary energy consumer. The efficiency advantages cited in most photonic compute papers measure only the optical core, not the mandatory analog-digital interfaces that surround it.

Implications:

• MZI meshes fail on Transformers — Reconfiguring MZI phases at token-rate timescales is thermally and control-limited; these architectures assume static weights and are structurally incompatible with dynamic attention mechanisms
• Time-multiplexed crossbar is the competitive architecture — Avoids MZI reconfiguration, achieves A100-competitive position in system-level benchmarks, surpasses B200 on energy efficiency
• Precision ceiling ~8 bits — Beyond this, efficiency collapses; brute-force precision scaling is unsustainable
• Peripheral overheads often exceed optical compute energy — Prior efficiency claims need re-measurement under full system accounting

This finding is recent enough (April 2026) that industry responses and follow-on work are not yet in this KB.

Open problems:

• What minimum DAC/ADC resolution preserves model accuracy for LLM inference?
• Can photonic architectures native to Transformer attention avoid the reconfiguration problem?
• What compilation tools exist to map standard ML models onto photonic hardware with correct system-level cost estimation?

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3. Photonic Compute Hardware — Accuracy Validated, Scale Not Yet

Status: Lab accuracy validated; scaling and manufacturing remain open Key sources: Nanophotonic Neural Network Sydney, Large-Scale Photonic Accelerator Nature, Fully-Programmable Photonic Processor Key players: University of Sydney, SJTU / TuringQ

Three 2025-2026 results establish that photonic chips can achieve practical accuracy on real tasks:

• University of Sydney: 90-99% classification accuracy on 10,000+ biomedical images at picosecond timescales (Nature Communications 2026)
• Nature 2025: 16,000+ component photonic chip benchmarks faster than GPU on specific workloads — largest-scale photonic accelerator demonstrated
• SJTU / TuringQ: 498-component chip achieves 97% MNIST accuracy AND 100% NP-complete problem accuracy on same hardware (7.22-bit precision)

The programmability milestone from SJTU is significant: one photonic chip, no hardware modification, handling both combinatorial optimization and neural network inference. This closes the argument that photonic chips are single-purpose inference engines — at least at 498-component scale.

What's not yet solved: manufacturing yield for 16,000+ component circuits; programming model for non-expert users; training (not just inference); and system-level efficiency under rigorous SimPhony-style accounting.

Open problems:

• Manufacturing yield for 16K+ component photonic circuits at wafer scale
• Software and compiler stack for deploying standard ML frameworks onto photonic hardware
• Can photonic accelerators handle training or only inference?
• What does the 16K-component chip look like under SimPhony system-level accounting?

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4. Quantum Photonics Convergence

Status: Steady research progress; QKD most commercially mature Key sources: Quantum Photonics on a Chip Key players: PsiQuantum, Xanadu (not yet in KB), Ben-Gurion University

Quantum photonics shares silicon photonics manufacturing infrastructure with classical photonic computing but operates in a fundamentally different regime — single-photon manipulation rather than coherent-field computation. The review by Katiyi and Karabchevsky (2025) synthesizes state-of-the-art across platforms, sources, and detectors.

Key status:

• SNSPDs >90% efficiency — Best detectors available, but require cryogenic operation (deployment-limiting)
• Quantum dots β ≈ 98% — Near-unity photon coupling into waveguides; still probabilistic emission
• Silicon photonics = preferred QKD platform — CMOS manufacturing compatibility for scalable quantum communication
• Room-temperature alternatives gap — SPADs at 65%, Ge APDs at 5.27% at 80K; order-of-magnitude below SNSPD

The commercial bridge is quantum key distribution (QKD): silicon photonic chips for quantum-secure communication are the most near-term application, requiring lower qubit counts than general quantum computing and directly leveraging the integrated photonics manufacturing base being built for classical CPO.

Open problems:

• Room-temperature single-photon detectors at >90% efficiency (would transform deployment economics)
• Deterministic single-photon sources (all current implementations are probabilistic)
• Heterogeneous integration of III-V emitters with silicon photonics at wafer scale

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Recent Breakthroughs (Compiled 2026-04-14)

Knowledge Gaps

Areas where the KB needs more sources:

• Intel silicon photonics — Intel has significant photonic integration investment; no KB coverage yet. Suggested search: "Intel silicon photonics foundry 2026"
• Lightmatter Envise photonic compute chip — Lightmatter's compute (vs. interconnect) product has only press release coverage in the KB; no technical details. Suggested search: "Lightmatter Envise photonic processor specifications"
• Software/compiler stack for photonic chips — How ML engineers map PyTorch/JAX models to photonic hardware; toolchains; no KB coverage. Suggested search: "photonic computing compiler stack neural network 2026"
• PsiQuantum / Xanadu quantum photonics — Major quantum photonics companies entirely absent from KB. Suggested search: "PsiQuantum silicon photonics 2026 progress"
• Broadcom photonic integration — Broadcom's CPO strategy and products; missing from entities. Suggested search: "Broadcom co-packaged optics CPO 2026"
• Luminous Computing — Photonic AI chip startup; not yet in KB. Suggested search: "Luminous Computing photonic chip 2026"
• System-level benchmarks post-SimPhony — Community response to UT Austin's findings; follow-on benchmarking work not yet captured