08LIGHT AS COMPUTE· SURGING

Optical Computing

Silicon photonics, co-packaged optics, photonic AI accelerators, optical neural networks

28SOURCES
7CONCEPTS
9ENTITIES
SOURCE MIX
15 P11 R2 A0 N
ACTIVITY · 20W
CPOPhotonicInterconnectSiPh

Optical Computing

The optical computing field in 2025-2026 operates on two timescales. The near-term story is co-packaged optics, and it now runs on two integration topologies. The chiplet model is locked in: Ayar Labs' $500M Nvidia-backed raise, TeraPHY at 200+ Tbps/package (5x Rubin GPU bandwidth), TSMC COUPE making optical I/O accessible to any TSMC customer via UCIe, and the OIF 3.2T multi-vendor standard. Alongside it, Lightmatter's Passage M-series puts optics into an active photonic interposer (the M1000: 114 Tbps total, 256 fibers, on-package optical circuit switching), and commercialization is shifting to ASIC/packaging partnerships — Lightmatter–GUC (Jan 2026) productizes Passage 3D CPO for hyperscalers. Deployment timeline: early adopters 2026, broader adoption 2027, standard AI networking by 2028.

The longer-term story is photonic compute itself — and 2026 delivered both a reality check and a breakthrough. The reality check: UT Austin's SimPhony framework shows DAC/ADC peripheral overheads dominate photonic AI energy budgets, MZI meshes fail on Transformer workloads, and practical precision is capped near 8 bits, with the time-multiplexed crossbar the competitive architecture. The breakthrough: Nokia Bell Labs demonstrated the first on-chip gradient-descent backpropagation — all linear and nonlinear computation on one photonic chip — retiring the "photonic chips are inference-only" assumption. Hardware demonstrations validate both accuracy and density (Sydney's peer-reviewed inverse-design accelerator: ~400M params/mm², 90-99% biomedical imaging; SJTU's 498-component chip: 97% MNIST + 100% NP-complete). The live design tension is now ultra-dense fixed-function accelerators (Sydney) versus reconfigurable on-chip-trainable processors (Bell Labs).

Frontier — What's Moving Now

  • CPO deployment wave underway, now two topologies — chiplet-CPO (Ayar Labs / TSMC COUPE / OIF) plus the active photonic interposer (Lightmatter M1000); commercialization via Lightmatter–GUC
  • On-chip training crosses the threshold — Nokia Bell Labs' on-chip gradient-descent backprop (Nature 651) ends the "inference-only" era at lab scale
  • DAC/ADC is the real bottleneck for photonic compute — SimPhony (April 2026) overturns prior component-level benchmarks
  • Density milestone — Sydney's peer-reviewed inverse-design accelerator hits ~400M trainable params/mm² (fixed-function)
  • Fixed-function vs. reconfigurable-trainable — the emerging design axis (Sydney ↔ Bell Labs)
  • Quantum photonics diverging — SNSPDs >90% efficient but cryogenic; silicon photonics the preferred QKD platform

Concept Map

Concepts

ConceptSourcesEvidenceFrontierLast Updated
Photonic Neural Networks9 (papers + reviews)StrongActive2026-06-24
Photonic Tensor Cores1 (paper)ModerateActive2026-04-05
Photonic Interconnects5 (tech reports + analysis)StrongActive2026-06-24
Co-Packaged Optics9 (tech reports + analysis + papers)StrongActive2026-06-24
Photonic Accelerators6 (papers + tech reports)StrongActive2026-06-24
Photonic Computing Limitations3 (papers)StrongActive2026-04-14
Quantum Photonics1 (review paper)ModerateActive2026-04-14

Entities

EntityTypeSourcesKey Connection
LightmatterCompany3Passage L200 (1.6 Tbps/fiber) + M1000 active interposer (114 Tbps) + GUC commercialization
Ayar LabsCompany3First UCIe optical chiplet, $500M raise, TeraPHY 200 Tbps/package
TSMC (Photonics)Foundry3COUPE platform: 100 Tb/s per accelerator
Nokia Bell LabsResearch1First on-chip gradient-descent backprop (Nature 651)
GUC (Global Unichip Corp)Company1Lightmatter's commercial Passage 3D CPO ASIC/packaging partner
OIFStandards Body13.2T CPO standard: 51.2 Tb/s switch bandwidth
Q.ANTCompany1NPU 2: 30x energy reduction (vendor claim), shipping 2026
University of SydneyResearch2Inverse-design nanophotonic NN: ~400M params/mm², 90-99% medical accuracy
UT Austin / ASU (SimPhony)Research1SimPhony: system-level benchmarking, DAC/ADC bottleneck

Timeline

See timeline.md for chronological developments (2019 through 2026).

Research Frontier

See frontier.md for active research directions, breakthroughs, and knowledge gaps.

Sources

#TitleTypeDateStatus
1Integrated Platforms for Photonic NNpaper2025-03-01compiled
2Neuromorphic Photonic Computing for AIpaper2025-06-01compiled
3Lightmatter Passage L200 Recordtech report2026-03-11compiled
4Ayar Labs UCIe Optical Chiplettech report2026-03compiled
5Photonics Shift for AI Data Centersanalysis2026compiled
6Nanophotonic Neural Network Sydneypaper2026-03-09compiled
7Large-Scale Photonic Accelerator (Nature)paper2025-06-01compiled
8Ayar Labs $500M Series Etech report2026-03-03compiled
9TSMC COUPE Silicon Photonicstech report2025-10-01compiled
10OIF 3.2T CPO Standardtech report2023-04-05compiled
11CPO Five Trends 2026analysis2026-02-05compiled
12Q.ANT NPU 2 Photonic Processortech report2025-11-19compiled
13Harnessing Photonics for Machine Intelligencepaper2026-04-12compiled
14Integrated Photonic Neuromorphic Computing Reviewpaper2025-09-01compiled
15Fully-Programmable Integrated Photonic Processorpaper2025-08-19compiled
16Quantum Photonics on a Chippaper2025-06-04compiled
17SKYLIGHT 3D WDM Photonic Tensor Corepreprint2026-02-26compiled
18LightIn Versatile Silicon Photonic Processorpreprint2026-04-01compiled
19Lightmatter Passage M1000 Superchiptech report2025-03-31compiled
20Lightmatter–GUC CPO Partnershiptech report2026-01-26compiled
21On-Chip Backpropagation PNN (Nature)paper2026-03compiled
22Inverse-Designed Nanophotonic NN Accelerators (Nat. Comm.)paper2026-03compiled