TSMC COUPE Platform for Silicon Photonics — Alchip + Ayar Labs Demo
Tech ReportTom's HardwareTSMC, Alchip, Ayar LabsOctober 1, 2025
Original SourceKey Contribution
First fully integrated COUPE-based optical I/O engine — 100 Tb/s per accelerator via UCIe interface
TSMC COUPE Platform — First Integrated Optical Connectivity Solution
Key Innovation
- COUPE (COmpact Universal Photonic Engine) — TSMC's standardized silicon photonics integration platform
- First fully integrated, in-package optical I/O engine built on COUPE
- Delivers up to 100 Tb/s of bandwidth per accelerator
- Connects to other chips using UCIe (Universal Chiplet Interconnect Express) standard
Architecture
- EIC-PIC integration — electrical IC and photonic IC co-packaged
- Minimizes coupling loss with low insertion loss for both grating and edge couplers
- EPIC-BOE platform features system-level integration of COUPE + COI + iFAU
- Enables CPO within 2.5D CoWoS environment — fits into existing advanced packaging
Ecosystem
- Alchip — ASIC design partner providing the electrical IC
- Ayar Labs — TeraPHY optical chiplet provider
- TSMC — foundry platform and packaging (COUPE + CoWoS)
- This is the first end-to-end demonstrated solution for optical I/O in AI chips
Significance
- Proves silicon photonics can integrate into standard TSMC packaging flows
- UCIe compatibility means any chiplet ecosystem participant can adopt optical I/O
- 100 Tb/s per accelerator eliminates bandwidth wall for next-gen AI training
- Path to all major AI chip companies (Nvidia, AMD, Google, etc.) using optical I/O
Source: TSMC COUPE optical connectivity — Tom's Hardware, 2025
Tags
TSMCCOUPEsilicon-photonicsUCIeco-packaged-optics