Co-Packaged Optics

Co-packaged optics (CPO) is the practice of integrating optical transceivers directly within the semiconductor package alongside compute dies, converting electrical signals to photons at the earliest possible point. The gain is not marginal — Nvidia's own testing showed link power drop from 30W to 9W transitioning from pluggable transceivers to CPO in 1.6T networks, a 70% reduction in data-movement energy. Since 60% of data center energy is spent on moving data rather than computing it, CPO is as much an energy story as a bandwidth one.

The architectural shift is fundamental. Traditional pluggable optics modules sit at the edge of switch ASICs and server cards, connected by centimeters of signal-degrading copper trace. CPO eliminates that path. Ayar Labs' TeraPHY chiplets deliver 8 Tbps per chiplet at 10-nanosecond latency; a reference design with 8 TeraPHY chiplets reaches 200+ Tbps aggregate bandwidth per package — roughly 5x the bandwidth of Nvidia's Rubin GPUs. At this scale, photonic interconnects don't just speed up communication; they change what AI cluster architectures are possible.

The standards layer is now locked in. The OIF's 3.2T Co-Packaged Module Implementation Agreement (2023) defined the first multi-vendor CPO module spec: 3.2 Tb/s per module, 8×400G optical interfaces, backward-compatible 50G lane signaling, enabling 51.2 Tb/s aggregate switch bandwidth. The CPO port market is projected to exceed 10 million units by 2029, with the photonic IC and laser market growing from $2.4B (2023) to $5.9B (2029). TSMC's COUPE (COmpact Universal Photonic Engine) platform and Ayar Labs' UCIe-compliant optical chiplet have closed the chiplet interoperability gap — any TSMC customer can now integrate optical I/O using standard chiplet interfaces.

A second integration topology is now in play alongside the chiplet model. Rather than placing optical engines as discrete chiplets next to compute, Lightmatter's Passage M-series puts optics into an active photonic interposer that the compute die complex stacks on top of: the M1000 is a >4,000 mm² multi-reticle interposer delivering 114 Tbps total optical bandwidth across 256 fibers, with electro-optical I/O routable anywhere on its surface and the first on-package solid-state optical circuit switching. Commercially, Lightmatter is routing this 3D-CPO line to AI hyperscalers through a January 2026 partnership with GUC (Global Unichip Corp), co-designing Passage 3D CPO into GUC's ASIC and advanced-packaging flow — a supply path parallel to the Ayar Labs → TSMC COUPE route, and a sign that the "physics is solved, manufacturing is the bottleneck" story is now being worked through commercial ASIC/packaging partnerships, not just standards.

The bottleneck has shifted from physics to manufacturing. Optical alignment requires micron-scale precision far exceeding electrical tolerances, thermal management of photonic ICs co-packaged with high-power logic dies remains unsolved at production volume, and the supply chain for InP lasers is constrained. These are engineering problems, not fundamental barriers — but they set the real deployment timeline.

Key Claims

• CPO cuts link power 30W → 9W — Nvidia internal testing on 1.6T networks shows 70% power reduction vs. pluggable transceivers. Evidence: strong (CPO Five Trends)
• 200+ Tbps/package achievable — Ayar Labs TeraPHY reference design with 8 chiplets, ~5x Rubin GPU bandwidth. Evidence: strong (Ayar Labs $500M)
• 100 Tb/s per accelerator via TSMC COUPE — First fully integrated COUPE-based optical I/O engine, UCIe-compliant. Evidence: strong (TSMC COUPE)
• OIF 3.2T standard enables multi-vendor interoperability — 51.2 Tb/s switch bandwidth, backward-compatible lane signaling. Evidence: strong (OIF 3.2T)
• Thermal management is the critical production blocker — Photonic ICs are temperature-sensitive; wavelength drift and laser degradation under co-packaged thermal gradients remain unsolved. Evidence: moderate (CPO Five Trends)
• CPO port market: 10M units by 2029 — Industry projection for deployment scale. Evidence: moderate (OIF 3.2T)
• Active photonic interposer as an alternative CPO topology — Lightmatter Passage M1000: 114 Tbps total, 256 fibers, on-package solid-state optical circuit switching; die complex stacks on the interposer rather than beside chiplets. Evidence: strong (vendor spec) (Lightmatter Passage M1000)
• Commercial 3D-CPO routed through GUC ASIC/packaging — Lightmatter + GUC (Jan 2026) target AI hyperscalers, extending scale-up across racks; supply-path analogue of Ayar Labs → TSMC COUPE. Evidence: moderate (Lightmatter–GUC Partnership)

Benchmarks & Data

• Ayar Labs TeraPHY: 8 Tbps/chiplet at 10ns latency (Ayar Labs $500M)
• TSMC COUPE: 100 Tb/s per accelerator (TSMC COUPE)
• OIF 3.2T module: 3.2 Tb/s, ~20×20 mm², 32W power draw (OIF 3.2T)
• Photonic IC + laser market: $2.4B (2023) → $5.9B (2029) (OIF 3.2T)
• CPO link power reduction: 30W → 9W on 1.6T networks (CPO Five Trends)
• Lightmatter Passage M1000: 114 Tbps total, 256 fibers @ 448 Gbps, >4,000 mm² 3D active interposer, 1.5 kW delivery (Lightmatter Passage M1000)

Deployment Timeline

• 2026 — Early CPO adopters in AI training clusters; Ayar Labs production samples; Q.ANT NPU 2 shipping
• 2027 — Broader 800G/1.6T adoption; TSMC COUPE ecosystem maturing
• 2028 — Photonic interconnects standard for AI-scale networking; 6.4T and 12.8T CPO generations emerging

Analyst View — Ramp Timing (Attributed, Unverified)

Dylan Patel (SemiAnalysis), on Podcast Alpha (2026-07-10), calls the real CPO ramp for 2029, two years later than the 2027 Street consensus implied by this page's own Deployment Timeline above. His stated reasoning: "Rubin and Feynman are all-copper" — i.e. NVIDIA's next two GPU generations retain copper interconnects rather than adopting CPO, pushing the commercial transition out. He names Amphenol (a copper-interconnect supplier) as the resulting beneficiary trade. Evidence: weak — Patel claims/estimates, unverified, no primary NVIDIA roadmap citation, disclosed conflict noted at source (SemiAnalysis is a reported Anthropic enterprise customer, relevant to his broader AI-infra commentary though not directly to this specific claim) (Dylan Patel / Podcast Alpha).

This directly contradicts the "2027 — Broader 800G/1.6T adoption; TSMC COUPE ecosystem maturing" line in this page's own Deployment Timeline, which was compiled from vendor/standards-body sources (OIF, Ayar Labs, Lightmatter, TSMC) rather than NVIDIA's own GPU roadmap. The gap is worth tracking explicitly: vendor supply-side sources say the ecosystem matures on a 2027 timeline; Patel says the actual buyer (NVIDIA, via Rubin/Feynman) isn't adopting CPO on that timeline at all.

Open Questions

• Does NVIDIA's Rubin/Feynman generation actually stay all-copper, as Patel claims? No primary NVIDIA roadmap source in this KB confirms or denies this.
• If Patel's 2029 call is right, does that delay ripple through to Ayar Labs/Lightmatter/TSMC COUPE commercial volume, or do those suppliers find non-NVIDIA (hyperscaler custom-silicon) demand in the interim?
• What is the cost premium of CPO vs. pluggable optics at production volume?
• Can photonic IC yield rates approach semiconductor norms at TSMC-scale manufacturing?
• Will UCIe optical standardization create a commodity CPO market, or will Ayar Labs / Lightmatter maintain differentiation?
• How does InP laser supply chain constrain total CPO deployment pace?

Related Concepts

• Photonic Interconnects — Broader interconnect technology context
• Photonic Accelerators — Compute chips that CPO feeds
• Photonic Neural Networks — AI workloads driving CPO demand

Changelog

• 2026-07-14 — Added Patel/Podcast Alpha attributed claim: real CPO ramp lands 2029 vs Street's 2027, attributed to Rubin/Feynman staying all-copper (Amphenol named as beneficiary trade) — unverified, flagged as contradicting this page's own vendor-sourced 2027 timeline.
• 2026-06-24 — Added the active-photonic-interposer CPO topology (Lightmatter Passage M1000, 114 Tbps / 256 fibers / on-package optical circuit switching) as an alternative to chiplet-style CPO, and the Lightmatter–GUC commercialization partnership (Jan 2026). 7 → 9 sources.
• 2026-04-14 — Initial compilation from 7 sources (April 8 ingestion batch)