Integrated photonic neuromorphic computing: device, architecture, chip, algorithm
Systematic multi-layer review of photonic neuromorphic computing spanning photonic neurons, synapses, network architectures, integrated chips, and optimization algorithms
Integrated photonic neuromorphic computing: device, architecture, chip, algorithm
Abstract
The paper presents a systematic review examining how optical-based neural computing can address computational limitations of traditional electronics. The authors emphasize that "photonic neuromorphic computing exhibits significant development potential" in the post-Moore era, particularly regarding overcoming memory and power constraints. The review covers photonic neurons, photonic synapses, network architectures, integrated chips, and optimization algorithms, while discussing future directions in device integration and practical applications.
Key Contributions
- Comprehensive synthesis of photonic neuromorphic device innovations, covering photonic neurons and synapses
- Documentation of photonic integrated circuit architectures for neuromorphic systems
- Analysis of algorithmic optimization approaches for optical neural networks
- Forward-looking assessment of integration and application expansion pathways
- Unified multi-layer framework spanning device, architecture, chip, and algorithm domains
Methodology
Systematic literature review synthesizing recent advances across device physics, chip architecture, and algorithmic domains within photonic neuromorphic computing. Organizes the field into a four-layer hierarchy: device (neurons/synapses) → architecture → chip → algorithm.
Results
Detailed benchmarks not available from abstract; paper synthesizes state-of-the-art results across photonic neuromorphic devices and systems, with the post-Moore era framing positioning photonic approaches as overcoming memory bandwidth and energy constraints of CMOS electronics.
Limitations
Specific limitations not detailed in the available abstract. As a review paper, primary limitations are those of the surveyed devices: analog precision, fabrication variability, and lack of mature training methodologies for hardware-aware photonic networks.
Source: Integrated photonic neuromorphic computing: device, architecture, chip, algorithm by Shuiying Xiang et al.
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