Advanced Packaging (CoWoS) Bottleneck

CoWoS (Chip-on-Wafer-on-Substrate) is TSMC's advanced-packaging process — the step that bonds GPU dies and HBM stacks onto a single interposer. It is the process that turns a wafer into a shippable accelerator, and per TSMC's Q2 2026 print it is sold out through the end of 2026, with lead times stretching into 2027. The N3 (3nm) node is reported sold out on the same horizon. This matters because it relocates the buildout's ceiling: a hyperscaler with capex approved and power secured can still be capacity-constrained if it is not already in TSMC's booked queue.

That is a second binding constraint sitting alongside power. The KB's founding thesis — see Power: The Binding Constraint — held that energized megawatts, not chips, gated the buildout. The TSMC data does not overturn that, but it complicates the clean "capital abundant, GPUs shipping, power scarce" framing that the 2026-06-24 compile recorded. As of mid-2026 the constraint set looks like packaging + memory + power simultaneously, with capital the only genuinely abundant input. Which of the three binds first for any given project is now a site-specific question rather than a topic-wide answer.

The commercial context: TSMC posted NT$1.27T (~$39.62B) revenue, +36% YoY — a record quarter, above its own $39.0–40.2B guidance band — and raised its full-year AI-segment revenue growth outlook to above 40%. CEO C.C. Wei: "Our conviction in the multi-year AI megatrend remains very high." Note the source is a single analysis piece covering the print; the underlying figures are TSMC's own but reach this KB secondhand, so every number here should be re-verified against TSMC's investor materials before it appears in published work.

Provenance caution. The concept now rests on two analysis-tier sources (Phemex on the print; TrendForce on capacity) — still no TSMC filing. A frequently-cited industry figure of 120–140K CoWoS wafers/month by end-2026 first appeared in Phemex's cross-reference section attributed to "separate analyst coverage"; TrendForce (a respected semiconductor research house) now independently corroborates that band, but it is still secondhand, not a TSMC disclosure. Treat capacity numbers as high-quality-secondary estimates, not filing-grade.

Capacity, quantified — the gap narrows but does not close (added 2026-07-23)

The prior compile had only the binary "sold out." A TrendForce report (2026-06-15) adds the capacity trajectory the frontier's "how fast does packaging ease?" question was missing:

• TSMC CoWoS capacity 2026: ~120,000–140,000 wafers/month (the ~130K target sits inside this band; a separate estimate cited ~127K by end-2026).
• OSAT partners (ASE et al.): +50,000–60,000 wafers/month of additional CoWoS-class capacity.
• Total industry advanced-packaging capacity target 2026: ~200,000 wafers/month.
• Supply-demand gap: ~20% now → ~10% by end-2026 — the shortfall is narrowing but not closed; demand still outruns supply through year-end.
• Trajectory: TSMC guided CoWoS capacity to >80% CAGR from 2022 to 2027 (May Taiwan Technology Symposium).
• Next-gen: NVIDIA's Feynman platform is the first CoPoS adopter, mass production 2028–2029 (Chiayi + Arizona) — beyond the current bottleneck window.

The load-bearing read: even with industry capacity quadrupling toward ~200K wafers/month, a ~10% supply-demand gap persists at end-2026 — so packaging stays a binding constraint through the year, not one that resolves. That is the answer to "how fast does packaging ease?": slowly, and not fully within 2026. All figures are TrendForce estimates as-of 2026-06-15 (projection/target bands, not audited realized output), and the KB's flagged need for a primary TSMC source on CoWoS remains open.

Key Claims

• CoWoS advanced-packaging capacity is sold out through end-2026, lead times into 2027. Evidence: weak (single analysis source reporting TSMC's print) (TSMC Q2 2026)
• N3 (3nm) node also sold out through end-2026. Evidence: weak (single analysis source) (TSMC Q2 2026)
• Packaging, not wafer starts, is the near-term ceiling on converting capex into installed GPU capacity. Evidence: weak (single-source interpretation) (TSMC Q2 2026)
• TSMC Q2 2026 revenue: NT$1.27T (~$39.62B), +36% YoY — a record, above the $39.0–40.2B guidance band. Evidence: weak (single analysis source; figures originate with TSMC but are secondhand here) (TSMC Q2 2026)
• [FORECAST] Full-year AI-segment revenue growth outlook raised to above 40%; gross margin guided 65.5–67.5%. These are company projections, not results. Evidence: weak (single analysis source, forward guidance) (TSMC Q2 2026)
• The constraint set is now plural — packaging + memory + power bind at once, with capital the only abundant input. Evidence: moderate (converging across TSMC, Samsung, and the existing power-bottleneck sources) (TSMC Q2 2026); (Samsung Q2 2026 preliminary); (Hyperscalers in 2026)
• CoWoS capacity figure (~120–140K wafers/month by end-2026) is NOT TSMC-stated — attributed to unnamed "separate analyst coverage" in Phemex, now corroborated by TrendForce but still secondhand. Evidence: weak→moderate (two independent analysis sources agree; no TSMC filing) (TSMC Q2 2026); (TrendForce CoWoS)

Added 2026-07-23 (capacity trajectory)

• TSMC CoWoS ~120–140K wafers/mo + OSAT 50–60K = ~200K industry wafers/mo target for 2026. Evidence: moderate (analysis — TrendForce, as-of 2026-06-15; projection/target bands) (TrendForce CoWoS)
• Supply-demand gap narrows ~20% → ~10% by end-2026 — but does not close; packaging stays binding through year-end. Evidence: moderate (analysis — TrendForce) (TrendForce CoWoS)
• [FORECAST] TSMC guided CoWoS capacity to >80% CAGR 2022–2027. Evidence: weak (analysis reporting a company guide, forward) (TrendForce CoWoS)
• [FORECAST] Next-gen CoPoS (NVIDIA Feynman) mass production 2028–2029 (Chiayi + Arizona) — beyond the current bottleneck window. Evidence: weak (analysis, long-horizon) (TrendForce CoWoS)

Benchmarks & Data

• TSMC Q2 2026 revenue: NT$1.27T (~$39.62B), +36% YoY (record)
• TSMC Q2 2026 guidance band: $39.0–40.2B (result came in above)
• Gross margin guidance: 65.5–67.5%
• [FORECAST] FY2026 AI-segment revenue growth: >40%
• CoWoS capacity: sold out through end-2026; lead times into 2027
• N3 node: sold out through end-2026
• CoWoS wafers/month: ~120–140K (TSMC) + 50–60K (OSAT) = ~200K industry target 2026 — quantified 2026-07-23 (TrendForce, secondary; no TSMC filing yet)
• Supply-demand gap: ~20% → ~10% by end-2026 (narrows, does not close); >80% CAGR 2022–2027
• Q2 net profit and Q3 guidance: not in source (pending full call at publication)

Open Questions

• What is TSMC's actual CoWoS capacity today and its committed end-2026 exit rate? Partly answered 2026-07-23 (TrendForce: ~120–140K TSMC + ~200K industry, gap 20%→10%) — but still no primary TSMC-sourced number. A TSMC filing/transcript remains the open target.
• Who holds the booked CoWoS queue? Allocation across NVIDIA, AMD, Broadcom, and hyperscaler custom silicon is unknown — and it determines who can actually deploy in 2027.
• Does packaging bind before or after power for a given project? The KB currently has no framework for sequencing the two constraints.
• Can CoWoS-L / SoIC / competing packaging (Samsung, Intel, Amkor, ASE) relieve the constraint, and on what timeline?
• Does "sold out through end-2026" mean capacity is fully allocated, or fully contracted with deposits? The distinction matters for how fast the queue could re-price if demand softened.
• What is the price trajectory of CoWoS capacity — is TSMC capturing the scarcity rent, or passing it to accelerator vendors?

Related Concepts

• HBM & DRAM Supply Tightness — the memory half of the same accelerator-supply constraint
• Power: The Binding Constraint — the competing (and, until this compile, presumed sole) binding constraint
• Rack Power Density — GB300 NVL72 racks are the deployment unit that CoWoS supply gates
• Hyperscaler Capex Cycle — approved capex cannot become installed capacity faster than packaging allows

Backlinks

Pages that reference this concept:

• TSMC
• Samsung

Changelog

• 2026-07-22 — Created from 1 source (tsmc-q2-2026-cowos-sold-out-through-2026). Opens a second binding constraint alongside power; complicates the prior "power is THE constraint" framing. All claims single-analysis-sourced — weak until a primary TSMC source is ingested.
• 2026-07-23 — Added the CoWoS capacity trajectory from TrendForce (2026-06-15): ~120–140K TSMC + 50–60K OSAT ≈ ~200K industry wafers/mo in 2026, supply-demand gap 20% → ~10% by end-2026 (narrows but does not close — packaging stays binding through year-end), >80% CAGR 2022–2027, CoPoS/Feynman 2028–29. Second independent analysis source corroborates the 120–140K band, upgrading it weak→moderate; a primary TSMC source still open.