TSMC

Type: Company (TSM) — Foundry and advanced packaging

TSMC is the chokepoint of the datacenters supply chain in a way that is easy to under-weight. It is not only where AI accelerators are fabricated (N3 and below) but where they are packaged — the CoWoS process that bonds logic dies to HBM stacks on an interposer. Per the single source in this KB, both CoWoS capacity and the N3 node are sold out through the end of 2026, with lead times into 2027. That makes TSMC's booked queue, not hyperscaler capex approval, the near-term determinant of who can actually deploy accelerators in 2027.

Commercially, TSMC's Q2 2026 was a record: NT$1.27T (~$39.62B) revenue, +36% YoY, above its own $39.0–40.2B guidance band, with the full-year AI-segment revenue growth outlook raised to above 40% and gross margin guided 65.5–67.5%. CEO C.C. Wei: "Our conviction in the multi-year AI megatrend remains very high."

This dossier is thin and weakly sourced. One analysis-tier piece is the entire evidentiary basis. The figures originate with TSMC but reach this KB secondhand; net profit and Q3 guidance were pending at publication and are not recorded here. Nothing on this page should be published without re-verification against TSMC's own investor materials. Confidence is deliberately set to low.

Key Facts

• CoWoS advanced-packaging capacity sold out through end-2026; lead times into 2027. Evidence: weak (single analysis source) (TSMC Q2 2026)
• N3 (3nm) node sold out through end-2026. Evidence: weak (single analysis source) (TSMC Q2 2026)
• Q2 2026 revenue NT$1.27T (~$39.62B), +36% YoY — a record, above the $39.0–40.2B guidance band. Evidence: weak (single analysis source, secondhand company figures) (TSMC Q2 2026)
• [FORECAST] FY2026 AI-segment revenue growth outlook raised above 40%; gross margin guided 65.5–67.5%. Company projections, not results. Evidence: weak (single analysis source) (TSMC Q2 2026)
• Named a supply-chain chokepoint alongside memory and power — the constraint set that gates conversion of capex into installed compute. Evidence: moderate (converging across three sources) (TSMC Q2 2026); (Samsung preliminary); (Hyperscalers in 2026)
• CoWoS wafers/month capacity figure (~120–140K by end-2026) is NOT TSMC-stated — attributed in-source to unnamed "separate analyst coverage." Unverified. Evidence: n/a (gap) (TSMC Q2 2026)
• Q2 net profit, Q3 guidance, segment/customer breakdown, capex plan: NOT in any ingested source. Evidence: n/a (gap)

Mentioned In

• Advanced Packaging Bottleneck — TSMC is the concept; CoWoS is its process
• HBM & DRAM Supply Tightness — HBM stacks and logic dies meet at TSMC's packaging step
• Rack Power Density — NVL72 rack deployment is gated by TSMC's booked queue

Related Entities

• Samsung — memory supplier into the same accelerator BOM; also a competing foundry
• Hyperscaler Buyers — their approved capex cannot convert to capacity faster than this queue allows
• Alphabet — custom silicon (TPU) competes for the same advanced-node and packaging allocation

Outstanding Questions

• Who holds the booked CoWoS queue — NVIDIA, AMD, Broadcom, hyperscaler custom silicon? Allocation determines 2027 deployment capability and is entirely unknown to this KB.
• What is TSMC's actual CoWoS capacity today and its committed end-2026 exit rate? No primary-sourced figure.
• Is TSMC capturing the scarcity rent in packaging pricing, or passing it through to accelerator vendors?
• Does competing packaging capacity (Samsung, Intel, Amkor, ASE) relieve the constraint, and on what timeline?
• Next action: ingest a primary TSMC source (quarterly report or earnings-call transcript) to replace this entirely secondhand dossier.