Reliability scaling is forcing memory intelligence regardless of commercial PIM adoption

Claim. Even if Processing-In-Memory never finds a broad production workload, DRAM cells at sub-3nm equivalent feature sizes are physically incapable of remaining "dumb." RowHammer, RowPress, and column-disturbance mechanisms already require on-die logic (DDR5 activation counters ship today). The trajectory from "defensive logic" → "autonomous management" → "general compute" is effectively unidirectional. Memory gains intelligence whether or not the industry chooses PIM.

Confidence. High (8/10). Physical disturbance mechanisms are peer-reviewed and exploited in the wild; DDR5 defenses are shipping; RowHammer paper won the 2024 Jean-Claude Laprie Award.

History.

• 2026-04-21 · 8/10 · Initial seed; RowHammer + RowPress evidence near-incontrovertible.

Key evidence.

• RowHammer (RowHammer is real), RowPress (arXiv:2406.16153), column disturbance — all demonstrated on commodity DDR4/DDR5.
• DDR5 standard includes activation counters; DDR6 drafts being watched.
• Self-Managing DRAM framework (MICRO 2024, Yaglikci/Luo/Mutlu) formalizes the trajectory.

What would invalidate it. A device-level breakthrough (e.g., different storage substrate — magnetic, ferroelectric, carbon nanotube) that displaces DRAM before the intelligence trajectory matures.

Author. Seeded 2026-04-21.