Rung 09 Networking & InterconnectSwitch rungClose
Networking & Interconnect
How chips and sites talk to each other.
Fourth-generation NVLink bandwidth per H100 GPU — what one accelerator can say to its neighbours
In scope: optical interconnect and co-packaged optics, scale-up versus scale-out fabrics, NVLink, InfiniBand and Ethernet economics, bandwidth per dollar, topology, cross-datacenter links. Out: memory bandwidth inside a package (hardware), photonic compute (out of the knowledge base entirely).
| Type | Source | Published |
|---|---|---|
| PAPER | Deep Neural Network Inference on an Integrated, Reconfigurable Photonic Tensor Processor Photonic tensor processor team · imec / silicon photonics ecosystem First production-ready photonic tensor processor for DNN inference — packaged in a 19-inch rack unit, PyTorch-integrated, MNIST + CIFAR-10 benchmarked. Runs pretrained networks without chip-specific retraining | 2026-01-15 |
| PAPER | Integrated Photonic Neural Network with On-Chip Backpropagation Training Farshid Ashtiani, Mohamad Hossein Idjadi, Kwangwoong Kim · Nokia Bell Labs First integrated photonic deep neural network with end-to-end on-chip gradient-descent backpropagation — all linear AND nonlinear computations on a single silicon photonic chip. 92.5% accuracy on 2D classification; automatically compensates for fabrication variations | 2026-03-20 |