ASML EUV monopoly
asml-euv-monopoly
- What: Extreme ultraviolet lithography — the only path to sub-3nm patterning.
- Who: ASML is sole global supplier. Sells ~60 EUV systems per year.
- Lead time: 18–24 months from order to install and qualify.
- Why it matters: No EUV → no leading-edge logic. Foundry node cadence is rate-limited by ASML ship schedule.
- Source: Hardware LENS; industry capacity data.
TSMC CoWoS bottleneck
tsmc-cowos-bottleneck
- What: CoWoS (Chip-on-Wafer-on-Substrate) — advanced packaging that integrates HBM stacks onto logic die.
- Who: TSMC holds near-monopoly; Amkor and Intel are ramping but years behind.
- Capacity: Binding constraint for NVIDIA/AMD AI chip supply 2025–2026. TSMC targeting ~2× expansion through 2026.
- Why it matters: You cannot ship an AI accelerator without CoWoS capacity. Cap on CoWoS = cap on AI GPUs.
- Source: Hardware theses T1 + T2; LENS supply-chain table.
HBM supplier hierarchy
hbm-supplier-hierarchy
- What: High-Bandwidth Memory — stacked DRAM that dominates AI training/inference throughput.
- Who: SK Hynix ≫ Samsung > Micron (by HBM3E/HBM4 capacity and design wins).
- Structural: HBM has materially higher gross margin than conventional DRAM; it's where memory cos bet the farm.
- Why it matters: SK Hynix's NVIDIA lock-in on HBM3E shaped 2024–2025 AI GPU pricing. HBM4 qualification is the 2026 battleground.
- Source: HBM4 Memory Architecture concept; SK Hynix + Samsung + Micron earnings disclosures.
Foundry tier
foundry-tier
- What: Leading-edge logic manufacturing (N2/N3/N5 nodes).
- Who: TSMC (dominant), Samsung Foundry (distant second on 2nm), Intel Foundry (trying).
- Share: TSMC commands the vast majority of AI accelerator foundry share (N3/N2 for NVIDIA, AMD, Broadcom).
- Why it matters: TSMC is the single point of failure for almost every frontier AI chip. Arizona and Kumamoto fabs are geopolitical hedges, not volume replacements.
- Source: Hardware LENS supply-chain table.
Advanced packaging diversification
advanced-packaging-diversification
- What: Packaging alternatives to TSMC CoWoS — Amkor, ASE, Intel Foveros.
- State 2026: All are ramping but none match TSMC on volume, yield, or customer trust for tier-1 AI chips.
- Why it matters: Until diversification arrives (~2027 earliest for meaningful share), AI-chip supply curve remains TSMC-shaped.
- Source: Hardware LENS.
Memory ↔ packaging coupling
memory-packaging-coupling
- What: HBM is useless without matched packaging capacity (CoWoS interposer for HBM-to-logic integration).
- Why it matters: You cannot independently expand HBM OR packaging — they have to scale together. Either becomes the binding constraint.
- Source: Hardware LENS; CoWoS + HBM expansion timelines.
Geographic concentration risk
geographic-concentration-risk
- What: Critical nodes cluster in Taiwan (TSMC), Korea (Samsung, SK Hynix), Netherlands (ASML).
- Why it matters: Single-geography failure (geopolitical, seismic, regulatory) can disrupt >50% of world AI compute supply. US CHIPS Act + Samsung Kumamoto + TSMC Arizona partially address but do not eliminate.
- Source: Hardware LENS; export-control regulatory context.
Export control overhang
export-control-overhang
- What: US export restrictions on advanced semiconductors and semiconductor equipment to China (2022–present).
- Effect: Cuts TAM for high-end AI chips in PRC; forces bifurcated product lines (H20, derated SKUs); accelerates China's domestic capacity push (SMIC, CXMT, YMTC).
- Why it matters: A structural governor on Western semi sales AND a forcing function for non-Western supply chain.
- Source: Hardware LENS forbidden-pattern note; export-control regulatory tracking.