SK hynix Ships Samples of 12-Layer Next-Gen 'HBM4E'
SAMPLES, NOT VOLUME: 12-layer HBM4E samples to major customers — up to 16 Gb/s per pin, 48 GB per stack, over 20% better power efficiency vs unnamed previous models, 17% better heat resistance vs HBM4; no mass-production date.
These are samples, not volume. A sample is a part sent to customers so they can test it in their own designs. It says the chip exists and works in the maker's hands; it says nothing about how many can be made, when, or at what price. SK hynix gives no date for mass production — only that it "will work closely with partners for mass production in a timely manner." Never cite anything below as supply.
How deeply this was read. The full press release, fetched directly from SK hynix's newsroom.
Whose claim this is. SK hynix's, about its own pre-production part. None of the figures has been checked independently.
What the release says
SK hynix "has shipped samples of HBM4E, a next-generation DRAM for AI, to major customers", describing the 12-high part as delivered "on schedule".
- Speed: "a maximum data processing speed of 16Gbps per pin".
- Power: "power efficiency that is up more than 20 percent from previous models" — the baseline ("previous models") is not named.
- Capacity: Advanced MR-MUF packaging lets it "achieve a 48GB capacity in a 12-layer stack". (MR-MUF is SK hynix's method of stacking dies by filling the gaps between them with a liquid protective material.)
- Heat: heat resistance "improved … by 17 percent, compared to the preceding HBM4".
- Latency: the release says the part "reduces data transfer latency" through its interface and design, but gives no number.
The release does not give a per-stack bandwidth, an interface width, a process node, a price, a customer name or a production date.
How it ties to the rung's numbers
Bandwidth per stack is the input that most directly sets how fast a GPU can produce tokens in the decode phase, and so what a token costs to make. This release moves the ceiling on that input in two ways, both still on paper:
- Pin speed. 16 Gb/s per pin is well above what the rung carried for HBM4E — the December 2025 analysis put HBM4E at 12 Gb/s with a 12.8 demonstration (HBM shakeup) — and above the "over 11 Gb/s" Micron ships in volume for HBM4 (Micron HBM4). Our arithmetic, not SK hynix's claim: if HBM4E keeps HBM4's 2,048-bit interface (the release does not say), 16 Gb/s per pin would be about 4.1 TB/s per stack. That would be above the 3 TB/s per stack the rung has quoted for HBM4E. Mark it [unverified] until a maker states it.
- Capacity per stack. 48 GB in 12 layers is the same capacity Micron reaches with HBM4 only by going to 16 layers (also samples). Fewer layers for the same capacity means denser dies.
The second value is simply that this is a second memory maker's view of the next generation, beside Micron's; the rung previously had one analysis article and no maker statement on HBM4E.
Limitations
- Samples only. No mass-production date, no volume, no price, no customer. It cannot move any supply or cost figure on this rung.
- Issuer claims, "maximum" speed. 16 Gb/s is the top rated speed of a sample, not a measured shipping figure.
- The 20% efficiency baseline is unnamed ("previous models"), so it cannot be compared cleanly with Micron's "over 20% versus our HBM3E".
- No per-stack bandwidth is given. Any TB/s figure for this part is derived, not quoted.
- Dated. State as of 18 June 2026.
Source: SK hynix, "SK hynix Ships Samples of 12-Layer Next-Gen 'HBM4E'", 18 June 2026.